1) Chip-select corresponds to memory bank. For one memory bank one chip-select has to be used.
2) Please refer to the AN3940 - Hardware and Layout Design Considerations for DDR3 SDRAM, Table 1. DDR3 designer checklist, 46:
"Ensure one clock pair is used for each chip-select. The clock pair should follow the address/command/control signal groups in fly-by topology."
3) The processor has four MODT[0: 3] signals. Each MODTn signal corresponds to specific chip-select - refer to the AN3940, Table 1. DDR3 designer checklist, 37:
" Connect each of the MODT signals that are in the same group to the same physical memory bank:
- MODT(0), MCS(0), MCKE(0)
- MODT(1), MCS(1), MCKE(1)
- MODT(2), MCS(2), MCKE(2)
- MODT(3), MCS(3), MCKE(3)"
4) You wrote:
> ? can I reverse the connection in those pins?
In the provided pictures connections are incorrect.
Please consider that DQS belongs to specific byte lane as specified in the AN3940, Table 1. DDR3 designer checklist, 25:
""Route all signals within a given byte lane on the same critical layer with the same via count. Assuming ECC
is used, the DDR3 data bus consists of nine data byte lanes.
Note: The byte ordering below is not a requirement; byte lanes can be routed in the order that best fits the
user’s application.
- Byte lane 0—MDQ(7:0), MDM(0), MDQS(0), MDQS(0)
- Byte lane 1—MDQ(15:8), MDM(1), MDQS(1), MDQS(1)
- Byte lane 2—MDQ(23:16), MDM(2), MDQS(2), MDQS(2)
- Byte lane 3—MDQ(31:24), MDM(3), MDQS(3), MDQS(3)
- Byte lane 4—MDQ(39:32), MDM(4), MDQS(4), MDQS(4)
- Byte lane 5—MDQ(47:40), MDM(5), MDQS(5), MDQS(5)
- Byte lane 6—MDQ(55:48), MDM(6), MDQS(6), MDQS(6)
- Byte lane 7—MDQ(63:56), MDM(7), MDQS(7), MDQS(7)
- Byte lane 8—MECC(7:0), MDM(8), MDQS(8), MDQS(8)"
