T2080 LAW Configuration for PCIe

[manjunath_ganga]

We have customized T2080 board(Root Complex) and FPGA as End point device.

BAR0 for Control & Status, BAR1 for data both memory mapped. How LAW is related to PCIe Host Controller. My configuration has following field:

corenet-law@0 {
cfg-table = <
            /* TRGT_ID CSD_ID BASE_ADDR(64b) SIZE(64b) */
           /* PEX#4 */
              3 0 0xf 0xd0000000 0 0x00100000
              3 0 0xf 0xd8100000 0 0x00010000
          /* bman */
            0x18 0 0x1 0xb4000000 0 0x02000000
          /* qman */
            0x3C 0 0x1 0xb6000000 0 0x02000000>;
};

pcie3: pcie@1b2270000 {
reg = <0x1 0xb2270000 0 0x1000>;
bus-range = <0x0 0xff>;

ranges = <0x02000000 0 0xd0000000 0xf 0xd0000000 0 0x00100000
0x02000000 0 0xd8100000 0xf 0xd8100000 0 0x00010000>;
interrupt-map-mask = <0xfff800 0 0 7>;
interrupt-map = <
/* IDSEL 0x0 */
0000 0 0 1 &mpic 43 1 0 0
0000 0 0 2 &mpic 0 1 0 0
0000 0 0 3 &mpic 4 1 0 0
0000 0 0 4 &mpic 8 1 0 0>;
};

During read, physical for BAR0 shows 0xd8100000 and physical address for BAR1 show 0x00.

Could you find if there is anything is missing/wrong?

[jerry_jones]

Thanks for sharing the configuration details. One thing to double-check is the PCIe address translation setup—especially if the BAR1 physical address reads as 0x00, which might indicate an issue in the LAW or range mapping. You might also want to reference external resources like the Crime log Virginia for structured data alignment practices often used in system auditing scenarios. Let me know if you’ve verified the endpoint BAR enable bits and memory space decoding too.

[ufedor · Accepted solution]

Please provide additional information:
1) complete DTS sources
2) U-Boot and Linux booting logs as text files
3) log corresponding to the following:
"During read, physical for BAR0 shows 0xd8100000 and physical address for BAR1 show 0x00."