T1040 Boot failure

[jboggs]

I have a T1040 based design configured to read the RCW and boot from a 16 bit NOR flash. Roughly 1 out of 100 times the processor won’t boot at power up. Using an oscilloscope I can see, after PORESET_B is released, HRESET_B never goes high, and there is no activity on IFC_CS0_B, so the processor is not attempting to read the RCW. I am not relying on internal pull up resistors for the CFG_RCW_SRC pins. I have CFG_RCW_SRC _3, CFG_RCW_SRC _6, CFG_RCW_SRC _7 and CFG_RCW_SRC _8 pulled up with 10k ohm resistors and CFG_RCW_SRC _0, CFG_RCW_SRC _1, CFG_RCW_SRC _2, CFG_RCW_SRC _4 and CFG_RCW_SRC _5 pulled down with 4.99k ohm resistors. Cycling PORESET_B low and high again will not take the processor out of this state, only another power cycle will resolve the issue. Do you have any idea what may be causing this issue? Is there another place I should be looking other than voltage rails at start up for an issue?

[jboggs]

OK, thank you very much for your help and your quick response. 

[jboggs]

Thank you for your quick response. It appears the problem is TRST_B is not held low during POR. That requirement was not clear to me from reading the documentation. I do have a few questions about some of the notes related to pin termination. The signals in question are described as “Reserved for Internal Use Only”, and they reference a note which says, “These pins must be pulled to ground”.  The data sheet does not offer any guidance as to the resistor value to use.    

The pins in question are:

Pin C20, FA_ANALOG_G_V

Pin B20, FA_ANALOG_PIN

The development board pulls these pins to ground with 698Ω.  Is that the best configuration for these pins? I have these pins tied directly to board ground, will that create a problem?

Pin F11, PROG_MTR

Pin G18, FA_VL

The development board pulls these to ground with a 330Ω resistor.  Is that correct for these pins?   I have these pins tied directly to board ground, will that create a problem?  

[ufedor]

All four signals can be directly connected to ground.

[ufedor]

It is required to check:

1) power sequencing (QorIQ T1040, T1020 Data Sheet, 3.2 Power sequencing)

2) TRST_B is pulsed asserted during POR (T1040 Family Design Checklist, Figure 25. JTAG interface connection)

3) PLL voltage supply filters are implemented as described in the T1040 Family Design Checklist, Table 4. Power design system-level checklist

4) termination of all signals having explicit notes in the QorIQ T1040, T1020 Data Sheet, Table 1. Pinout list by bus and use a digital scope to check POR levels of all there signals.