T1024CE A-009885 Questions

[MarkPalamar]

Hi,

I'm trying to implement the suggested workaround for erratum A-009885 on the T1024 platform.   The document states that when MDIO_DATA returns FFFFh, the read sequence should be repeated ensuring that the time between MDIO_CTL configuration and reading MDIO_DATA is less than 80 x MDC clock period. (assuming that MDIO_CFG[PRE_DIS] is 0)

When I looked at uboot source code (file memac_phy.c , function memac_mdio_read, I noticed that after MDIO_CTL is written, it immediately starts polling MDIO_DATA, looking for MDIO_DATA_BSY to clear.  MDIO_DATA_BSY (1<<31).

This BIT is not documented as valid in the T1024DPAARM (however it is referenced in other QorIQ products as valid).

I had been polling the MDIO_CFG register's busy bit before reading from MDIO_DATA.  I switched my code to follow what uboot was doing and found that it functioned the same way, taking about the same time to read valid data from MDIO_DATA after writing to MDIO_CTL.

Question 1: is polling MDIO_DATA[MDIO_DATA_BSY] as uboot is doing valid?

Question 2: In the erratum workaround description, should the time between writing to MDIO_CTL and reading from MDIO_DATA measure the time between writing MDIO_CTL and the first read of MDIO_DATA (as uboot code is doing), or should it only measure the time between writing to MDIO_CTL and the first valid read from MDIO_DATA (after polling either MDIO_STAT_BSY or MDIO_DATA_BSY)?

The total time between writing to MDIO_CTL and reading valid data from MDIO_DATA seemed to take about 11.3 usecs.  I calculated 80 x MDC clock period to be about 12.9 usecs  (In this case FMAN frequency 500MHz, MDIO clock divisor 0x28, so MDIO clock frequency 500000000/(0x28*2 + 1) = 6172839).

In order to retry the read sequence during runtime, we would need to disable interrupts for up to 12.9 usecs which is a very long time.

However, if the answer to Question 2 is the time between writing to MDIO_CTL and doing a read from MDIO_DATA (even if not valid yet), then the time needed to have interrupts disabled would be much less.

Thanks,

Mark

[MarkPalamar]

As a follow up question, the workaround description states: "During the T2-T1, the process reading the MDIO_DATA could be interrupted by interrupt or be prompted by higher priority process which breaks the time conditions. In this case, the interrupt needs to be disabled to make sure the process is not interrupted."

Does this mean that if interrupts are disabled throughout the process the issue will not occur?  For example, during initialization we do some initial configuration of the PHY and interrupts are disabled at this time, so should that code be safe from this erratum?

[r8070z]

A1  I had read report that one checks the kernel and uboot code and found that both of then use two ways to check MDIO BUSY. For the T1024 we should check the documented busy bit.

A2  If MDIO_CFG[BSY] is set then read data is invalid. So we should wait for the read transaction end in any case. Erratum say definitely “The above conditions are to ensure that the time between MDIO_CFG[BSY]=0 (after configuring MDIO_CTL) and reading MDIO_DATA register is less than 16 x MDC clock period.”

A3  It does not mean that if interrupts are disabled throughout the process the issue will not occur. It means that due to interrupt the MDIO_DATA may not be read in time.