we are using DDR4 with T1022 processor. In App-note AN5097_rev.1, it is given that "The clock signal trace length from the memory controller to any given DDR4chip should be longer than its corresponding strobe trace length."
In further sections it is also given that " In the case that the clock trace length is shorter, the following limits must be observed: The clock trace length can be a maximum of 2.0 inches shorter than the strobe trace length for a given byte lane."
presently my clock length is shorter than longest strobe by 1 inch. is it okay, or should I increase my clock's length?
I also heard of write leveling for such issues. How much skew can we compensate by that?
I also want to now that, in this write leveling, we adjust (DELAY) clock or we adjust (Advance) MDQS?
Is it a byte wise adjustment (means we adjust MDQS and clock for each 8 byte lanes differently) or a single adjustment for all 8 data byte lane?