Please refer to the following testing code:
#ifdef DDR_MBE
li r3,0x0003 //set 2 inject bits
#endif
lis r4,DDR_DATA_ERR_INJECT_LO@h
ori r4,r4,DDR_DATA_ERR_INJECT_LO@l
bl write_mmap
lis r3,DDR_ECC_ERR_INJECT@h
ori r3,r3,DDR_ECC_ERR_INJECT@l
bl read_mmap
ori r3,r3,(DRR_ECC_ERR_INJECT_EIEN)@l //set EIEN
lis r4,DDR_ECC_ERR_INJECT@h
ori r4,r4,DDR_ECC_ERR_INJECT@l
bl write_mmap
sync //store a line from L1D into DDR while error inject is enabled
dcbf r0,r8
msync
//clear DDR error inject
lis r3,DDR_ECC_ERR_INJECT@h
ori r3,r3,DDR_ECC_ERR_INJECT@l
bl read_mmap
lis r4,DRR_ECC_ERR_INJECT_EIEN@h
ori r4,r4,DRR_ECC_ERR_INJECT_EIEN@l
andc r3,r3,r4 //clear EIEN
lis r4,DDR_ECC_ERR_INJECT@h
ori r4,r4,DDR_ECC_ERR_INJECT@l
bl write_mmap
xor r3,r3,r3
lis r4,DDR_DATA_ERR_INJECT_LO@h
ori r4,r4,DDR_DATA_ERR_INJECT_LO@l
bl write_mmap
Have a great day,
TIC
-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------