Detailed description is provided in the AN4261 - P2020 QorIQ Integrated Processor Design Checklist, Table 27. Ethernet Pin Recommendations, TSEC2_TXD[05]/TSEC3_TX_EN:
"TSEC2_TXD[05] is a POR configuration pin for eSDHC card-detect (cfg_sdhc_cd_pol_sel) and also has an alternate function as TSEC3_TX_EN. When eTSEC1 or eTSEC2 or eTSEC3 are used as parallel interfaces, pins TSECx_TX_EN requires an external 4.7-k pull-down resistor to prevent PHY from seeing a valid Transmit Enable before it is actively driven. However, the pull-down resistor on TSEC3_TX_EN cause the eSDHC card-detect (cfg_sdhc_cd_pol_sel) to be inverted, the inversion should be overridden from the SDHCDCR [CD_INV] debug control register.
If the chip is configured to boot from eSDHC interface, SDHC_CD should be inverted on the board."
The SDHCDCR is described in the P2020 QorIQ Integrated Processor Reference Manual, 21.4.22 SDHC debug control register (GUTS_SDHCDCR).