The reason for using an individual clock for each SerDes clock input is to achieve the input specification mentioned in section# 3.23.2 of the LS1046A datasheet as using the same clock to multiple inputs might create a condition where the input specs of the input clock might not be achieved.
For the LS1046, it is not necessary to use four external SERDES clock generators to utilize all of the transceivers. You can use a single clock generator with multiple outputs to provide the required reference clocks for the SERDES lanes. This approach will help you save PCB area and simplify the design.
However, it is essential to ensure that the clock generator you choose can provide the necessary frequencies and phase relationships required by the SERDES lanes. You can refer to the LS1046 data sheet and reference manual for the specific clock requirements for each SERDES lane: