RCW Hard coded settings in P2040

[ebyjayan]

Hi,
We are currently using P2040 processor with Hard coded RCW settings to boot the board.
While doing this, we are implementing two switch settings - one for fresh board and other for the programmed board.
Followings are our doubts:-
1.) Can we use a single hard coded option for a fresh board as well as for programmed board. (Note: by programmed board we mean to say that our flash drives contains the binaries for booting)
2.) In continuation of the 1st doubt, suppose if the first option is possible, whether we can use NOR for our PBL and NAND for our Boot LOC where NOR is located by hard coded RCW switch settings and RCW word will direct ti NAND flash for BOOT_LOC.
3.) Its a general question, what should be our best implementation such that we can use NOR for storing PBL and rest binaries in NAND for 2 stage booting.

[ufedor]

1) Theoretically it is possible, but it is needed to consider that hard coded RCW options have relatively low platform and core PLL ratios which usually are insufficient.

2)  You wrote:

> and RCW word will direct ti NAND flash for BOOT_LOC.

Sorry, this statement is not clear.

3) There is no hardware limitation preventing described booting sequence.

It is up to the software developer to initialize NAND FCM in PBL for the 2nd stage booting.

[ebyjayan]

Hi fedor,

Thank you very much for your responses. In addition to your responses, I would like to add some more queries.
1.) Suppose if I am using the binary - '10010' (as marked below), I will get 14:1 PLL ratio. 

Please suggest what should be the adequate PLL ratio.

2.) As you told that theoretically first option is possible, so consider the below implementation :-
   A.) My PBL is stored in NOR flash which is represented by '10010' Hard coded settings and this will be used for both - fresh board as well as already programmed board.
   B.) My Boot_SRC says the location NAND and my 2nd stage booting files are stored in the NAND.
whether above implementation is possible?

3.) If you look into the P2040 reference manual, it says  -  (as marked below)

Please suggest, how we can use NOR and NAND simultaneously in our implementation.

[ufedor]

The RM is talking about RCW + PBL - not about 2nd stage booting.

It is up to the software developer to initialize NAND FCM in PBL for the 2nd stage booting.

[ebyjayan]

Hi Fedor,
We were discussing with people from NXP through Avnet, and they confirmed in mail that

But, as you mentioned earlier that it is possible to implement PBL and U-boot in NOR and NAND respectively if the software is able to initialise the NAND in PBL.
Please confirm the same by giving any implementation example or any supporting document.
Thanks for you support in advance.

[ufedor]

Possible configuration/sequence is:

1) RCW+PBI+SPL(Secondary Program Loader) are in NOR, U-Boot in NAND

2) running from NOR, SPL initializes SDRAM and FCM and loads U-Boot from NAND to SDRAM

[ebyjayan]

Hi Fedor,
Thanks for your clarification. 
One more doubt we have.
Is it possible to make any GPIO accessible at PBL stage only, that is, we can toggle the GPIO when we are at PBL booting stage and after PBL stage no one can access that GPIO.
Also, NOR (GPCM) doesn't has any dedicated Write protect signal, which GPIO can be used to achieve this (write protect) functionality. 

[ufedor]

Please create new community thread for new questions.