Hi!
I have a FPGA connected to my LS1046A via PCIe and wish to have it write to processor RAM. That works, but the processor cache is not invalidated and the processor continue to read the buffer cache image. According to the RM the PCIe lanes are connected to the CCI via slave interface S1.
Our general question is:
- How to enable cache coherency for memory transfers from a FPGA to processor RAM.
The current state of our investigation is:
The Snoop enable bit in Snoop Control Register S1 is not defined.
- Does that mean that cache coherency from that CCI slave interface is not possible?
The approach is to set the DVM enable bit in Snoop Control Register S1. That has not been possible even after enabling non-secure access (Secure Access Register[Secure_Access_Control] is set).
Observing that Snoop Control Register S1[Support_DVMs] is not set we realize that Snoop Control Register S1[Enable_DVMs] cannot be set, as Snoop Control Register S1[Support_DVMs] is an "input". RM, and ARM documentation, refer to signal ACCHANNELEN but no other info on that has been found.
- Does Snoop Control Register S1[Support_DVMs] = 0 imply that cache coeherency via DVM is not possible via S1?
We believe that some other unit (PEX, TBU1 or Interconnect Fabric (IF)) has settings that allow DVM support via S1, but we cannot find any. So, in the end, we'd like to try turning Snoop Control Register S1[Support_DVMs] on to enable DVM support via S1.
- How do we turn Snoop Control Register S1[Support_DVMs] = 1?
Can you help us?
Regards
/Per
