PCIe interface from P4080DS

[appalanaidug]

Hello,

We are trying to interface P4080DS board with FPGA board through PCIe

The FPGA board is configured as end-point(EP) and P4080DS is configured as RC. We have connected the FPGA board to PCIe slot 1 of P4080DS.

U-boot log shows that the FPGA board is detected.

PCIe1: Root Complex, x2 gen1, regs @ 0xfe200000
01:00.0 - 10ee:6018 - Memory controller

The cmd "pci header " shows the following data

=> pci header 01.00
vendor ID = 0x10ee
device ID = 0x6018
command register ID = 0x0006
status register = 0x0010
revision ID = 0x00
class code = 0x05 (Memory controller)
sub class code = 0x00
programming interface = 0x00
cache line = 0x08
latency time = 0x00
header type = 0x00
BIST = 0x00
base address 0 = 0xe0000000
base address 1 = 0x00000000
base address 2 = 0x00000000
base address 3 = 0x00000000
base address 4 = 0x00000000
base address 5 = 0x00000000
cardBus CIS pointer = 0x00000000
sub system vendor ID = 0x10ee
sub system ID = 0x0007
expansion ROM base address = 0x00000000
interrupt line = 0xff
interrupt pin = 0x01
min Grant = 0x00
max Latency = 0x00

When we are trying to access data from "base address 0 = 0xe0000000" using "mmap" function in linux user space, some random data is being read.

We request your help on the following points

1. Is "base address 0 = 0xe0000000" correct address to access fpga data?

2. Any address mapping or kernel driver settings required?

3. Steps to access EP data from linux user space.

Thank you in advance.

[ufedor]

> 1. Is "base address 0 = 0xe0000000" correct address to access fpga data?

Not correct, because this address is on the PCIe bus and it has to be generated by translating a P4080 local address.

Correct base address in the P4080 address space can be determined from the PCIe1 Outbound Windows registers dump (CCSR range 0xfe200C00-0xfe200C9F).

[appalanaidug]

Hello,

Thankyou for the reply.

The following is the log of Outbound window registers

fe200c00: 00000000 00000000 00000000 00000000 ................
fe200c10: 80044023 00000000 00000000 00000000 ..@#............
fe200c20: 000e0000 00000000 00c00000 00000000 ................
fe200c30: 8004401c 00000000 00000000 00000000 ..@.............
fe200c40: 00000000 00000000 00ff8000 00000000 ................
fe200c50: 8008800f 00000000 00000000 00000000 ................
fe200c60: 00000000 00000000 00000000 00000000 ................
fe200c70: 00000000 00000000 00000000 00000000 ................

wherein 

fe200c20 (PEX1_PEXOTAR1) : 000e0000

fe200c28 (PEX1_PEXOWBAR1) : 00c00000

When I try to access address 0xc0000000 from linux user space, as shown below,I get "segmentation fault" 

#define PCI_addr 0xC0000000

data = *(unsigned long*)(PCI_addr+0x00);

Please clarify the following points:

1.  Does "base address 0 = 0xe0000000" from "pci header" correspond to PEX1_PEXOTAR1?

2. Is the address "0xC0000000" from PEX1_PEXOWBAR1 correct address to access pcie data?

3. How to check if the address "0xC0000000" is mapped to LAW of PCIe1 of P4080DS( commands if any to check the same from u-boot terminal is requested.)

The u-boot log is attached for reference

Thank you in advance.

[ufedor]

Please try to change the LAW size to 256 MB instead of current 512.

[appalanaidug]

Hello,

Thank you for the reply.

I changed the LAW size to 256MB from 512MB as suggested, from u-boot terminal using "mm" command as shown

fe000c50: 0000000c 00000000 8000001c 00000000 ................

=> mm fe000c58
fe000c58: 8000001c ? 8000001b

After updating LAW size, log is as shown

fe000c50: 0000000c 00000000 8000001b 00000000 ................

Even after modification, when I access 0xc0000000 from linux user space, I get "segmentation fault"

1. Can the LAW size be updated from u-boot terminal using "mm" command

2. Is the LAW register at "fe000c50" corresponds to PCIe1 of p4080ds board.

Any help is requested.

Thank you in advance.

[ufedor]

> 2. Is the LAW register at "fe000c50" corresponds to PCIe1 of p4080ds board.

No.

The corresponding LAW is:

fe200c20: 000e0000 00000000 00c00000 00000000 ................
fe200c30: 8004401c 00000000 00000000 00000000 ..@.............

Answers to the previous questions:

> 1.  Does "base address 0 = 0xe0000000" from "pci header" correspond to PEX1_PEXOTAR1?

Yes.

> 2. Is the address "0xC0000000" from PEX1_PEXOWBAR1 correct address to access pcie data?

No.

> fe200c28 (PEX1_PEXOWBAR1) : 00c00000

This corresponds to the 0xC_0000_0000

[appalanaidug]

Hello,

Thank you for the help.

On accessing the "0xC_0000_0000"  with "mmap64", I could access the data through PCIe.

One more question regarding LAW and Outbound ATMUs

1. How do  (LAW_LAWBARHn/LAW_LAWBARLn) and outbound windows (OWBARn) differ in functionality?

Thank you in advance.

[ufedor]

Please consider that LAW only attribute a local memory region to a specific interface/controller, while Outbound ATMU performs address translation from internal address space to PCIe.