P2041 hardware bring up issues

[wxwangyan]

I'm debugging  a customer P2041 board.

There're issues in P2041 boot up stage,  following test cases:

Test case1: cfg_rcw_src[0:4]配置字 01100 (Nor flash 8bits width)， elbc bus output LCLK0 signal at 6.25MHz, elbc cs0 will output four valid chip select signals ( but p2041rdb output eight chip select signals  under this case)

Test case2: cfg_rcw_src[0:4]配置字 01101 (Nor flash 16bits width)， elbc bus output LCLK0 signal at 6.25MHz, elbc cs0 will output two valid chip select signals ( but p2041rdb output four chip select signals  under this case)

Test case3: cfg_rcw_src[0:4]配置字 10000 (hardcode rcw)，RESET_REQ_B is always assert high level '1', it seems the cpu is always at reset status.

Test case4: cfg_rcw_src[0:4]配置字 00110（SDHC)， dessert PORESET_B,  SDHC_CLK and SDHC_CMD will output some signal

Can any one give me some suggestion at these conditions?

[wxwangyan]

updated  these test cases:

Test case3: cfg_rcw_src[0:4] 10000 (hardcode rcw)，RESET_REQ_B is always assert high level '1', it seems the cpu is always at reset status,  HRESET is always at low level "0", Asleep is at high "1".

Test case5: cfg_rcw_src[0:4] 00000 (I2C normal), program I2C eeprom with rcw word , after cpu loaded rcw word from eeprom ,  the HRESET is also at low level "0", Asleep is at high "1". It seems p2041 halt at rcw configuration stage.

Test case1: cfg_rcw_src[0:4]配置字 01100 (Nor flash 8bits width)， elbc bus output LCLK0 signal at 6.25MHz, elbc cs0 will output four valid chip select signals ( but p2041rdb output eight chip select signals  under this case),.

In test case1 ,because elbc bus output LCLK0 signal at 6.25MHz,  Does it mean the clock tree for elbc ok?

Can you give me any suggestion to check it?

[ufedor]

It is required to doublecheck the processor connection schematics and confirm (by means of a digital scope) levels of  signals (at the PORESET low->high edge) having note 31 in the P2040 QorIQ Integrated Processor Hardware Specifications, Table 1. Pin List by Bus.

[ufedor]

You wrote:

> elbc cs0 will output four valid chip select signals ( but p2041rdb output eight chip select signals  under this case)

Ensure that correct RCW is present in the NOR Flash.

Described behaviour corresponds to the case when PBL is unable to detect a correct preamble - refer to the P2040 QorIQ Integrated Multicore Communication Processor Family Reference Manual, 5.4.3 Required Format of Data Structure Consumed by PBL.

> RESET_REQ_B is always assert high level '1'

High level corresponds to the deasserted state of the signal ("_B" means active low).

[wxwangyan]

Test case5: cfg_rcw_src[0:4] 00000 (I2C normal), program I2C eeprom with rcw word , after cpu loaded rcw word from eeprom ,  the HRESET is also at low level "0", Asleep change to  high "1" at the end of load I2C eeprom. But MCKE, MCK is always at low "0".

The behaviour corresponds to following   Some of the I/O drivers are enabled; specifically, those pins associated with any interface potentially usable as the source of RCW data. All of the DDR I/Os become
enabled at this point (though MCKE, MCK, MODT are enabled from the beginning).
The ASLEEP signal is also enabled at this point.

P2040 QorIQ Integrated Multicore Communication Processor Family Reference Manual,   4.6.1 Power-on reset sequence     stage 8.