P2020 input clock specifications

cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 

P2020 input clock specifications

688 Views
toddreed
Contributor I

What are the P2020 input clock specifications when taking oscillator tolerance into account?

1)  System clock:  Max spec is 100MHz.  If using a 100MHz oscillator with +/-100ppm drift, does that violate the max limit?

2)  DDR input clock:  Min spec is 66.7MHz.  If using a 66.67MHz oscillator with +/-100ppm drift, does that violate the max limit?

3)  SGMII clock:  SGMII transmit and receiver Unit Interval spec is 800ps +/-100pm.  Does this mean the SGMII input clock must be within +/- 100ppm?

Thank you,

Todd

Tags (1)
0 Kudos
1 Reply

643 Views
Bulat
NXP Employee
NXP Employee

1,2) No, it does not violate.

3) Yes, Serdes reference clock should be within +/- 100ppm if SGMII is used.

Regards,
Bulat

0 Kudos