P2020 eTSEC clocks needed for SGMII connection

[dank4]

i want to connect the P2020 eTSEC to an SGMII interfaced phy (88e1512) , 

which clocks should i be connecting at the P2020 , 

these i am sure of :

• P2020 sys clock  - V
• P2020 serdes lanes - sd ref clk - V

but about this one :

• do i need to clock the eTSEC clock input as well - ? 

Thanks ahead 

[ufedor]

> do i need to clock the eTSEC clock input as well - ?

No - refer to the P2020 QorIQ Integrated Processor Reference Manual, Table 14-1. eTSECn network interface signal properties:

"EC _GTX_CLK125

Oscillator source for GMII, TBI, RGMII, RTBI transmit clock, input, shared by all eTSECs"