P2020 SYSCLK

cancel
Showing results for 
Search instead for 
Did you mean: 

P2020 SYSCLK

234 Views
michaelkachalov
Contributor I

Hello,

There seems to be some discrepancy in the Freescale documentation regarding the frequency for the P2020 SYSCLK frequency.

In AN4261 rev4, Table 10 states the SYSCLK pin must always be connected to an input clock of 66 - 100 MHz. However, in the P2020 datasheet rev2, the minimum SYSCLK frequency is specified at 64 MHz. Additionally, the Integrated Ref Manual rev2 12/2012 in section 4.5.3.19 states that we can use a frequency below 66 MHz as long as we take care of the cfg_sys_speed register on power up.

So is it okay to go below 66 MHz?

Thanks

Tags (2)
0 Kudos
1 Reply

102 Views
alexander_yakov
NXP TechSupport
NXP TechSupport

Yes, it is ok to have SYSCLK in range from 64 to 100 Mhz, as specified in Hardware Specifications, Table 8

Have a great day,
Alexander

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

0 Kudos