For P2020NXE2KHC / P2020EC Rev. 3, I do not see evidence that NXP provides a VDD-pin-by-pin or Core0/Core1 percentage power breakdown. The available data should be treated as aggregate rail-level power , not as an allocation to individual VDD balls or to specific cores.
What is documented:
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Item
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What the documentation provides
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VDD pins
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The 34 VDD balls are listed collectively as “VDD — Core Supply” ; they are not divided into VDD1…VDD7 for Core0 and VDD8…VDD34 for Core1 in the datasheet pin table.
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AVDD_CORE0 / AVDD_CORE1
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These are identified as Core PLL0 Supply and Core PLL1 Supply , at pins F15 and F16 respectively.
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Core power table
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Table 5 gives P2020 Core Power Consumption at defined frequency, VDD, junction temperature, and power mode conditions; for example, at 1.05 V and 125 °C, maximum power is listed from 6.1 W at 800 MHz up to 7.2 W at 1333 MHz.
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Scope of Table 5
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NXP support clarified that the Table 5 P2020 core power value is for both cores , not one core to be doubled.
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I/O power
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Table 6 provides estimated I/O power by interface/block, such as DDR, PCI Express, eLBC, eTSEC, serial RapidIO, SGMII, eSDHC, USB, eSPI, DUART, I²C, and GPIO.
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Per-pin data
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NXP support documentation explicitly states: “We don't have nor plan to generate per pin power values for these parts.”
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So, for your example question — “VDD1 to VDD7 account for xx% for Core0, VDD8 to VDD34 for Core1, AVDD_CORE0 for xx%, AVDD_CORE1 for xx%” — the answer is: that allocation data is not available in the retrieved NXP documentation/support material . The VDD balls should be considered a common core supply network, not separately specified per core or per pin. This is also consistent with an NXP P2020 reference schematic note stating that, for P2020, all VDD pins are common for both single- and dual-core devices .
Your reasoning is physically reasonable: with one core at 100% utilization and the other at 50%, the instantaneous internal current distribution inside the die will not be perfectly uniform. However, the published P2020EC data does not expose that internal distribution. For board-level power design, regulator sizing, PDN, and thermal analysis, use the total VDD/AVDD core power from Table 5 plus the applicable I/O power estimates from Table 6, rather than trying to assign percentages to individual VDD pins or cores.
Takeaway: NXP provides aggregate P2020 core-rail power, not a per-VDD-pin or Core0/Core1 percentage breakdown; treat all VDD pins as the common core supply and design from the total Table 5 power values.
