Hi,
Thanks for the information. I have changed the attached files for adding NAND support. The changes are tagged under /*** ARICENT ***/.
Kindly confirm whether following configurations are fine in P1020_SKU.h,
#define CONFIG_SYS_NAND_BASE 0xd0000000
#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define NAND_MAX_CHIPS 1
#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_CMD_NAND 1
#define CONFIG_NAND_FSL_ELBC 1
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
/* NAND flash config */
#define CONFIG_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE_PHYS \
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
| BR_PS_8 /* Port Size = 8 bit */ \
| BR_MS_FCM /* MSEL = FCM */ \
| BR_V) /* valid */
#define CONFIG_NAND_OR_PRELIM (0xFFF80000 /* length 32K */ \
| OR_FCM_CSCT \
| OR_FCM_CST \
| OR_FCM_CHT \
| OR_FCM_SCY_1 \
| OR_FCM_TRLX \
| OR_FCM_EHTR)
#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
#define CONFIG_SYS_BR1_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */
#define CONFIG_SYS_OR1_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
cpu_init_nand.c :
out_be32(&lbc->br1, CONFIG_NAND_BR_PRELIM);
out_be32(&lbc->or1, CONFIG_NAND_OR_PRELIM);
With the above configurations, in "NAND info" u-boot command, NAND device ID is displayed. But in "nand read", it is displaying "skipping bad block" with error read failed.
In Linux, the probe function in freescale NAND ELBC driver is failed in mapping the memory region. The dmesg log is "failed to get memory region".
Kindly confirm whether NAND base address is fine to map in Linux.
Thanks & Regards,
S.Abinesh.