Hi,
I am trying to implement a scheduler on a QorIQ T1022 that relies on nested interrupts - a timer interrupt to run the frame periodically and a second, nested, timer interrupt as a deadline timer to detect overrunning tasks within the frame.
To the core these are both IVOR4 external interrupt exceptions. So in order to allow a nested occurrence the exception/interrupt handling sequence is as follows:
- Store processor context
- Read the MPIC IACK register to determine the interrupt source
- Set the core MSR[EE] bit to re-enable base level exceptions
- Call the appropriate handler for the interrupt source
- Write to the MPIC EOI register to signal the end of the interrupt
Our expectation was that when we set MSR[EE] this would allow a nested interrupt to occur if its priority is higher than the one being currently handled but what we see is the nested interrupt being held off until the write to EOI at the end of the sequence.
