NOR FLASH how to work

[cai_tx]

I have one question abount NOR FLASH

On C29x_PCIE Demo board，NOR flash address is between 0xec000000 and 0xefffffff,we can run u-boot on the nor flash,when I flash rom on the nor flash ,I want to know how u-boot works? where is the PC pointer?

and why pc point to nor flash?

[alexander_yakov]

The e500 core does not have PC pointer.

After reset, the e500 core always starts from fixed address 0x0_FFFF_FFFC.

But, this is "Effective address", not physical address. so, if you wish to start from different address, you can prepare translation page to translate this effective address to another location. By default this is not used, boot page is translated directly.

Please look C29x Reference Manual, Section 4.3.3 "Boot page translation" for details.

Have a great day,
Alexander

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[amarnathmb]

Hi,

I have a similar issue, We have a custom board with T2080RDB as reference.
Once core 0 is booted can i make other cores to boot from DDR address?

Is it possible to change the boot location of other cores using Boot Space Translation registers?

Regards,

Amar

[scottwood]

The same Boot Space Translation is visible by all cores.  So yes, you can use it to direct secondary cores to DDR when they come out of reset.

[amarnathmb]

Hi,

Could you please clarify me what does 'nnn' in address 0x0_FFFF_Fnnn mean (section 4.3.3 Boot Space Translation of T2080RM Rev 0, 11/2014)?

From RM :

"When each core comes out of reset, its MMU has one 4 KB page defined at

0x0_FFFF_Fnnn. Each core begins execution with the instruction at effective address

0x0_FFFF_FFFC. To get this instruction, the core's first instruction fetch is a burst read

of boot code from effective address 0x0_FFFF_FFC0. For systems in which the boot

code resides at a different address, the chip provides boot space translation capability.

Note that boot space translation affects transactions initiated by all cores in the same

manner."

Does it mean that each core will jump to different boot page address after coming out of reset? But from my understanding instruction at reset vector 0xFFFFFFFC will always jump to boot page at last 4KB offset (0xFFFFF000), then what is the significance of 'nnn'. Please clarify me if I'm wrong?

Regards,

Amar

[scottwood]

It is both an effective address and a physical address -- the initial TLB entry is hardcoded to be an identity mapping.  Boot page translation happens at the physical address level.  During a normal independent boot (i.e. not controlled by PCI host or similar), the boot page is not translated during boot, and the flash is accessible at the top of the 32-bit address space.  0xec000000 is just where U-Boot chooses to relocate flash to once it's running.

[addiyi]

Before uboot relocate itself in DDR, PC will point to NOR addresses. Please take a look on AN4876, Chapter 5 to see how uboot works and to find out the uboot stages.

Adrian