NAND boot for P1011RDB

[rolfa]

Hi,

we are considering using a QorIQ P1011 in a new design.
The product should boot using U-Boot stored in NAND flash.
In order to learn how this works, I have read the manuals and
looked at the U-Boot code for the P1011RDB board. It looks like
this board can be compiled with support for NAND boot:
$ make P1011RDB_NAND_config
$ make all

This works fine, but the resulting u-boot-nand.bin file is
almost 400 000 bytes. As far as I know, this file must be copied
to the L2 cache (used as SRAM) by the nand_spl code.
What I can not understand, is how this can work as the as the size
of the L2 in P1011 is 256K.

Looking at include/configs/P1_P2_RDB.h, it seems that NAND boot is only
supported for CPUs with L2 size of 512K. This makes sense considering
the size of u-boot-nand.bin file, but in that case the P1011RDB_NAND_config
target should have been removed.

Is NAND boot supported for P1011RDB?
If yes, where have I misunderstood?

[suchit_lepcha]

Yes NAND boot is supported in P1011RDB.

The NAND boot essentially works in three stages:

Stage I) If eLBC-FCM is selected as the boot ROM controller from power-on-reset configuration, eLBC will automatically load from bank 0 a single 4 Kbyte page of boot code into the FCM buffer RAM during HRESET. The reset vector of the core is directed to FCM buffer. The core starts execution from FCM buffer, initializes core, configures L2 cache as L2 SRAM, copies a small part of code from FCM buffer to L2 SRAM and jumps execution to L2 SRAM.

Stage II) The core executes from L2 SRAM, configures DDR controller, copies complete u-boot from NAND to DDR and jumps to DDR. This stage is required because the FCM buffer RAM is used for copying boot-loader from NAND to DDR. The code residing the L2 SRAM is very small. For your information, in 83xx devices, 16k L1 i-cache was used for this stage.

Stage III) Execute from DDR.

Hope this answers your query.

[mattsm]

Actually, the P1011 has less than 512kB of L2 SRAM. However, it can still NAND boot it just skips the middle L2 step (for the time being anyways). It copies itself from NAND to DDR after configuring DDR directly out of Stage 1.

[scottwood]

Three-stage boot as Suchit describes was proposed (on mpc85xx/QorIQ, not

mpc83xx), but the implementation was not finished.  On chips where L2 cache is

too small (or absent), DDR is normally initialized in the first stage (as Matthew describes)

using fixed register values (the code to process SPD data won't fit in

that stage) -- but it looks like this is not currently supported by

P1_P2_RDB.  So no, NAND boot is not yet supported on P1011RDB.

BTW, do you have the -PC variant of the P1011RDB?  In that case, p1_p2_rdb_pc is the config you want, and that does support going straight to DDR from the NAND SPL.  You'd build for the P1020RDB-PC_NAND target (or P1020RDB-PC_36BIT_NAND).  P1020 is the same as P1011 except with two cores.  I suspect that it will work and that the difference in the number of CPUs will be detected at runtime, but it's possible you could run into problems.  Again, this will only work if you have the -PC variant of the board.

[mattsm]

Sorry, I thought P1011 was a P1010 variant - but Scott is correct it's using the older P1_P2_RDB. Are you sure this is what you want? These are older, please check the variant as Scott suggested.