LX2160A L3 cache flush

[Eco56]

Dear Sirs,

I am trying to run sel4 tests (sel4test) on a LX2160ARDB system. Currently, sel4test cache tests fail, and it looks I need to be able to flush the L3 cache to have them to succeed. How can I do it? Can I simply map CCN-58 register space to mmio and perform the flush by a procedure similar to the one that exists in NXP U-Boot (__asm_flush_l3_dcache)?

Best regards

Eco56

[Oswalag]

Hello,

I haven't tested sel4test before but, according to the U-boot code https://github.com/nxp-qoriq/u-boot/blob/lf_v2024.04/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S you can use it as example to flush L3 cache. 

The L3 memory system consists of the HN-F protocol node in the CCN-508, it means L3 cannot be flushed using CPU instructions, it requires writing to CCN registers and changing power states (pstate) of the HN-F nodes, of course it also requires MMIO access to CCN registers.

for more information you can refer to the ARM®
CoreLink™ CCN-508 Cache Coherent Network Revision: r0p1 Technical Reference Manual .