Hi, We have a LS2085ARDB devkit with us and we wanted to regenerate the binaries, which mainline kernel and uboot we should be using?
Another question is we wanted to tftp the board and we get following error, what could be wrong.
e1000: e1000#0: ERROR: Valid Link not detected
Following is the uboot console log,
U-Boot 2015.01Layerscape2-SDK+g16c10aa (May 14 2015 - 15:17:11)
SoC: LS2085E (0x87010010)
Clock Configuration:
CPU0(A57):1800 MHz CPU1(A57):1800 MHz CPU2(A57):1800 MHz
CPU3(A57):1800 MHz CPU4(A57):1800 MHz CPU5(A57):1800 MHz
CPU6(A57):1800 MHz CPU7(A57):1800 MHz
Bus: 600 MHz DDR: 1866.667 MT/s DP-DDR: 1600 MT/s
Reset Configuration Word (RCW):
00: 48303830 48480048 00000000 00000000
10: 00000000 00200000 00200000 00000000
20: 00c12980 00002580 00000000 00000000
30: 00000e0b 00000000 00000000 00000000
40: 00000000 00000000 00000000 00000000
50: 00000000 00000000 00000000 00000000
60: 00000000 00000000 00027000 00000000
70: 412a0000 00000000 00000000 00000000
Board: LS2085E-RDB, Board Arch: V1, Board version: D, boot from vBank: 0
FPGA: v1.18
SERDES1 Reference : Clock1 = 156.25MHz Clock2 = 156.25MHz
SERDES2 Reference : Clock1 = 100MHz Clock2 = 100MHz
I2C: ready
DRAM: Initializing DDR....using SPD
Detected UDIMM 18ASF1G72AZ-2G1A1
Detected UDIMM 18ASF1G72AZ-2G1A1
DP-DDR: Detected UDIMM 18ASF1G72AZ-2G1A1
19.5 GiB
DDR 15.5 GiB (DDR4, 64-bit, CL=13, ECC on)
DDR Controller Interleaving Mode: 256B
DDR Chip-Select Interleaving Mode: CS0+CS1
DP-DDR 4 GiB (DDR4, 32-bit, CL=11, ECC on)
DDR Chip-Select Interleaving Mode: CS0+CS1
Waking secondary cores to start from fff1b000
All (8) cores are up.
Using SERDES1 Protocol: 42 (0x2a)
Using SERDES2 Protocol: 65 (0x41)
Flash: 128 MiB
NAND: 2048 MiB
MMC: FSL_SDHC: 0
EEPROM: Invalid ID (ff ff ff ff)
PCIe1: disabled
PCIe2: disabled
PCIe3: Root Complex x1 gen1, regs @ 0x3600000
01:00.0 - 8086:10d3 - Network controller
PCIe3: Bus 00 - 01
PCIe4: Root Complex no link, regs @ 0x3700000
In: serial
Out: serial
Err: serial
Error! Not a FIT image
SATA link 0 timeout.
AHCI 0001.0301 32 slots 1 ports 6 Gbps 0x1 impl SATA mode
flags: 64bit ncq pm clo only pmp fbss pio slum part ccc apst
Found 0 device(s).
SCSI: Net: crc32+
fsl-mc: Booting Management Complex ... SUCCESS
fsl-mc: Management Complex booted (version: 7.0.3, boot status: 0x1)
fsl-mc: Deploying data path layout ... SUCCESS
e1000: 68:05:ca:36:90:df
DPNI10, DPNI8
Error: DPNI8 address not set.
, DPNI1, DPNI2
Error: DPNI2 address not set.
, DPNI3
Error: DPNI3 address not set.
, DPNI4
Error: DPNI4 address not set.
, DPNI7, DPNI9
Error: DPNI9 address not set.
, e1000#0 [PRIME]
Warning: e1000#0 MAC addresses don't match:
Address in SROM is 68:05:ca:36:90:df
Address in environment is 68:05:ca:2e:24:ee