LS146A - Generic timer initialization

[Chris_Avery]

Attempting to initialize the system timer on a custom LS1046A board. The reference manual states the CNTFID0 (0x2b0_0020) register is undefined at reset and allows read/write access, but I can not write to the register. This is the first thing the software attempts to initialize at power-on. Does anyone know if there is some other interface that needs to be setup before this register can be written? 

[yipingwang]

my understanding is that you have to set the enable bit in the control register and make sure that the write access is in the EL3.

[Chris_Avery]

Thank you for answering me, but I had no luck with your suggestion. Assuming you meant the counter enable bit in CNTCR at 0x2b0_0000.

After verifying I was in EL3 I tried setting the Control register enable bit and it made no difference in the ability to write the CNTFID0 register. Nothing I do seems to change the contents of the CNTFID0 register.

I'm wondering if this is why I can't find an example writing to this register in uBOOT either.

If my initial assumption about the enable bit was wrong (i.e. I set the wrong enable bit), please let me know what enable bit you were referring to.

Thank you again.

[yipingwang · Accepted solution]

Please refer to the following in ATF source code plat/nxp/soc-ls1046/soc.c

/*******************************************************************************
* Function to set the base counter frequency at
* the first entry of the Frequency Mode Table,
* at CNTFID0 (0x20 offset).
*
* Set the value of the pirmary core register cntfrq_el0.
******************************************************************************/
void set_base_freq_CNTFID0(void)
{
/*
* Below register specifies the base frequency of the system counter.
* As per NXP Board Manuals:
* The system counter always works with SYS_REF_CLK/4 frequency clock.
*
*/
unsigned int counter_base_frequency = get_sys_clk()/4;

/* Setting the frequency in the Frequency modes table.
*
* Note: The value for ls1046ardb board at this offset
* is not RW as stated. This offset have the
* fixed value of 100000400 Hz.
*
* The below code line has no effect.
* Keeping it for other platforms where it has effect.
*/
mmio_write_32(NXP_TIMER_ADDR + CNTFID_OFF, counter_base_frequency);

write_cntfrq_el0(counter_base_frequency);
}