LS1046A Reference Manual doubts

[almudena_martin]

I need clarification about one doubt after reading LS1046A Reference Manual:

LS1046 DDR Controller provides a clock signal DDRCLK (pin J20) . According to LS1046ARM, this signal is the reference clock to the DDR PLL and the configuration of the DDR PLL is done with Clocking_PLLDGSR  register (DDR PLL general status register).  In this register, it is necessary to set KILL bit = 0 to enable PLL performance and configure CFG field to fix the PLL multiplier where CFG field reflects the values programmed in RCW[MEM_PLL_RAT].

But according to Table 4-14 of LS1046ARM, MEM_PLL_RAT of RCW register configures the DDR PLL : SYSCLK ratio.

I understand that DDRCLK and SYSCLK are different clock signals. So , is DDR PLL obtained from DDRCLK or from SYSCLK?

Thank you in advance

[ufedor]

RCW[DDR_REFCLK_SEL] selects which clock will be used as a source for the DDR PLL - refer to the QorIQ LS1046A Reference Manual, Figure 4-3. Single Oscillator Source Clocking

[almudena_martin]

According to Figure 4-3 and Table 4-14 of Reference Manual, by configuring DDR_REFCLK_SEL it can be used DDRCLK or DIFF_SYSCLK.

On the other hand, MEM_PLL_RAT of RCW register configures the DDR PLL : SYSCLK ratio.  So, is this ratio  referenced to SYS_CLK or DIFF_SYSCLK? 

[ufedor]

For the MEM_PLL_RAT SYSCLK and DIFF_SYSCLK is the same notion.

[almudena_martin]

Thank you for your response.

I still have doubts about this, could you please clarify me the following assumptions and doubts? 

1) DDR PLL can be obtained from DDRCLK or DIFF_SYSCLK by configuring RCW[DDR_REFCLK_SEL]. If DDR_REFCLK_SEL = 00 then DDRCLK is reference clock. If DDR_REFCLK_SEL = 01, DIFF_SYSCLK is reference clock. Is there any restriction about configuration  or recommended configuration of the reference clock? 

2) RCW[MEM_PLL_RAT] configures the DDR PLL:SYSCLK ratio. In case DDRCLK clock is selected, I assume that RCW[MEM_PLL_RAT]  ratio is applied to DDRCLK, is this correct?

As an example of this, DDRCLK is selected (DDR_REFCLK_SEL = 00) and 100 MHz external clock is used. If it is configured  RCW[MEM_PLL_RAT] =00_1111 (15:1), then DDR PLL frequency results 1500 MHz. Is this correct?

Thank you in advance

[ufedor]

1) There are no restrictions.

It is up tot he designer which clock to use.

2) Both statements are correct.

[almudena_martin]

Thank you very much for all your help.

Now all is clear.

[almudena_martin]

Thank you very much for your help.

According to this, clock reference for DDR PLL can be DDRCLK or DIFF_SYSCLK.