[LS1046A] Inquiries regarding clocks

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[LS1046A] Inquiries regarding clocks

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Contributor I

To whom may it concern.

 

Hello I'm HS.

 

I've been working on designing the board referenced LS1046ARDB and FRWYLS1046.

The board does not include CPLD nor MCU, quite similar to FRWY.

 

Q1. System clock.

There are two different system clocks - Differential and single ended one.

Datasheet denotes that you can choose either diff or single ended one.

I'll opt for differential clocks.

But i saw single and diff. clocks are still connected to the respective pins in both LS1046ARDB and FRWYLS1046.

Do we need to input these clocks to diff. and single clock pins even though you don't use one of them?

Or can we omit one of them? (Screenshot below is from LS1046ARDB.)

20200918_133734.jpg

 

Q2. SerDes, DDR clocks.

Do clocks which go into SerDes and DDR have to synchronize with system clock?

I'm wondering if they have to synchronize with another clock.

If they don't need to synchronize with any clock, would it be possible to use XTAL/VCTCXO as a source of DDR or SerDes Clock?

 

Q3. 1588

One of my main goals is to obtain clear 1588 pulse from LS1046A.

What should we do to boost the quality of 1588 pulse with respect to jitter?

I assume that if Pin AC1(TSEC_1588_CLK_IN) is applied with 125MHz, then Pin AE1(TSEC_1588_PULSE_OUT1) and AF3(TSEC_1588_PULSE_OUT2) source the 1PPS.

Am i correct?

Does this 125MHz synchronize with some other clocks to improve the integrity?

I would really appreciate if you elaborate how to get good quality of 1588 1PPS and how LS1046A process it.

 

Q4. Does AQR107 in LS1046ARDB have something to do with 1588 1PPS?

 

Thank you.

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4 Replies

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NXP TechSupport
NXP TechSupport

1) Which SYSCLK to use - differential or single ended - is up to the board designer.

To chose the one please refer to the QorIQ LS1046A Reference Manual, 4.4.7 Clocking.

2) The clocks are asynchronous.

3) Parameters of the TSEC_1588_CLK_IN are provided in the QorIQ LS1046A, LS1026A Data Sheet, 3.10.8.2 IEEE 1588 AC timing specifications.

You wrote

> Does this 125MHz synchronize with some other clocks to improve the integrity?

This is not required.

4) No.

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53 Views
Contributor I

To whom may it concern.

 

I posted several questions.

 

When can i expect to hear from you?

 

Thank you

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90 Views
Contributor I

Thank you for your reply!

 

I really appreciate you help. 

 

I've got more questions tho..

 

Q1. Is there reason LS1046ARDB chose to use LS1046A for time-stamping as to 1588?

10G PHY(AQR107 in this case) can time-stamp as well. I wonder why you rather use LS1046A than AQR107.

 

Q2 Do we need to apply external signals for 1588? What would be the signals?

 

 

I'm afraid you forgot to answer one of my previous questions.

 

Q3. 1588

One of my main goals is to obtain clear 1588 pulse from LS1046A.

What should we do to boost the quality of 1588 pulse with respect to jitter?

I assume that if Pin AC1(TSEC_1588_CLK_IN) is applied with 125MHz, then Pin AE1(TSEC_1588_PULSE_OUT1) and AF3(TSEC_1588_PULSE_OUT2) source the 1PPS.

Am i correct?

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45 Views
NXP TechSupport
NXP TechSupport

A1) It is up to the board designer which device to use for PTP implementation.

For NXP implementation please refer to the LSDK Documentation:

https://docs.nxp.com/bundle/GUID-51EEFEDB-ABD5-40C0-BEBD-6527B3494D57/page/GUID-15E89810-0E59-4F13-8...

A2) At a minimum - no.

A3) Clock source for the 1588 timer is selected in the FMan register TMR_CTRL[CKSEL] (QorIQ LS1046A Data Path Acceleration Architecture (DPAA) Reference Manual, 7.4.3.2.1 Timer Control Register (TMR_CTRL)) and it could be as high as MAC system clock - i.e. up to 800 Mhz (refer to the QorIQ LS1046A, LS1026A Data Sheet, Table 140. Processor, platform, and memory clocking specifications).

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