LS1046 ECn_GTX_CLK125 Rise/Fall TImes

[matthej]

Hi,

In the LS1046 datasheet it lists the ECn_GTX_CLK125 rise and fall times as .75ns max.

The PHY I am planning on using specs the rise and fall times of its output clock to be 1.5ns:

Will the LS1046 operate correctly with this device?

Thanks!

[ufedor]

ECn_GTX_CLK125 has the time period of 8ns. If we take 40%-40% duty cycle, we have 8*0.4 = 3.2ns for high and low cycle time and total 6.4ns. Remaining time is used by rise and fall time of signal i.e. 8 - 6.4 = 1.6ns. In normal case it is possible to use clock buffer only if the combine rise and fall time is not greater than 1.6ns. For example, you can have (rise time, fall time) as (0.8ns, 0.8ns) or (1.0ns, 0.6ns).

In the described case the timing balance will be significantly affected, so normal operation of the RGMII interface cannot be guaranteed.

[matthej]

Thanks for your response.

In addition, I have the following two questions:

The PHY datasheet shows the test conditions used to measure the rise/fall times. 

1) Does NXP have a test circuit which was used to measure the rise/fall times?

2) Can an external clock be used to provide the ECn_GTX_CLK125? Can it be asynchronous to all other clocks?

Thanks!

[ufedor]

1) No, because the ECn_GTX_CLK125 is applied to the processor - thus timings are specified at the processor side.

2) You wrote:

> Can an external clock be used to provide the ECn_GTX_CLK125?

Yes.

> Can it be asynchronous to all other clocks?

Yes.

[matthej]

So we are running this interface at 10/100Base T and not 1000BaseT.

I am assuming that this would make a difference in the rise/fall times specifications since the interfaces do not use the same clocking interface (DDR vs regular)?

Thanks!

[ufedor]

Your understanding is correct.

[matthej]

Do you happen to know what these new values would be if running 10/100?

[ufedor]

When running 10/100 Mbps rise and fall timings are not specified because the clock period is big enough.

[matthej]

But isn't the clock period the same for 10/100/1000?

In other words, isn't the LS1046 expecting still a 125MHz clock regardless of the rate we are running at?

[ufedor]

Good starting point is to read RGMII Specification.

[matthej]

Hi Udefor,

I am familiar with the RGMII spec, however, the ECn_GTX_CLK125 is not part of the RGMII spec as it is a reference clock.

Since this has to be 125MHZ to the LS1046A device, I can't see where the relaxation of the rise and fall times can occur since we are using 10/100 instead of 1000baseT as we are still sending the 125MHZ clock (and not the 25MHz or 2.5MHz clock in the case of 10/100). With that said, I would think the same rise/fall times would still apply despite using 10/100 only.

Furthermore, the PHY used on the LS1046ARDB eval board does not specify the rise/fall time for this clock (CLKOUT) so I am not sure how this board is meeting its specification. It specifies the RGMII interface as .75ns but not CLKOUT.

Can you pleas answer these questions?

Thanks!

[ufedor]

In the RGMII Specification is is written:

"For 10Mbps and 100Mbps, Tcyc will scale to 400ns+-40ns and 40ns+-4ns respectively."

[matthej]

That spec is referring to the tx and rx clock on the rgmii interface and not the ecn_gtx_clk125. The ecn_gtx_clk125 is fixed at 125MHz according to the ls1046 datasheet so the mention of reduced clock rates doesn’t seem to apply here.  There is no mention of this 125MHz clock in the RGMII spec.

I hope I am wrong here….

 Thanks!