LS1043a QSPI RX/TX messages larger than 128 bytes

[Alexandre-SCHMITT]

Hi,

I want to use the QSPI controller to send and receive messages to a specific chip.
The frames between this chip and my LS1043a need to be bigger than 128 bytes whitout CS rising up.

Is there a method to pop the  RX buffer when the IDATSZ value is higher than 128 bytes?

What I am doing today with a flash memory to test a read of 4ko at one time :

1- Init of the QSPI Controller
2- Unlock the LUT
3- Progam the LUT4 with : INST0 : CMD , OP0 : 0x03, INST1 : ADDR, OP1 : 0x18
4- Progam the LUT5 with : INST0 : READ, OP0 : 0x00, INST1 : 0x00 , OP1 : 0x00
5- Lock the LUT
6- RBCT -> Use IP
7- SFAR -> 0x40000000
8- IPCR[SEQID] = 0x01, IPCR[IDATSZ] = 0x1000 (4ko)
9- I can read all (32) RBDRn
10- How to pop RBDRn? And read the following 128 bytes and others?

Thanks,

Alexandre SCHMITT

[yipingwang]

qSPI in LS1043a has a hardware limitation of RX FIFO length of 128 Bytes. There is no method to pop the RX buffer when the IDATSZ value is higher than 128 bytes. The maximum value for WMRK is 31, which works with 128 Byte data. The Read/Write operations involve access the FIFO buffers and then to the external slave devices.
Is any particular reason why it cannot use a frame size of 128 Bytes? The FlexSPI controller in LX2160 SoC can have 1 KBytes FIFO.