Proper operation of the RGMII bus requires careful control of the timing relationship between clock and data signals.
The LS1043A Data to clock input skew (at receiver) implies that PC board design will require clocks to be routed such that an additional trace delay of greater than 1.5 ns is added to the associated clock signal. Many PHY vendors already incorporate the necessary delay inside their device. If so, additional PCB delay is probably not needed.
Try to use via as less as possible on RGMII interface traces to minimize the timing skew. Keep RGMII interface traces less than 6 inches long, minimizing the interface timing skew.
It’s advised to keep the difference of the traces lengths less than 400 mils among the TX and the RX part.
