LS1043A Event Processor EVT Pin Control Register

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LS1043A Event Processor EVT Pin Control Register

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frank_o
Contributor III

Hi,

On LS1043A, we are trying to set the DIR bits of the Event Processor EVT Pin Control Register (EPEVTCR0) 0 to 9.

Based on LS1043a Reference manual Rev 6, these registers are in the DCSR region with EPU base address=0x60000 and offset 0x50 for EPEVTCR0. So the full address should be 0x20060050. But writing to this register and reading back always return's 0.  We tried to do this with PBI commands and u-boot without success.

Also, there was an update in revision 6 of the LS1043A Reference Manual, where they say DCSR_BASE to be 0x07 0000 0000.  Based on Table 2-1. System memory map, I believe this address is for another LS version, but would like confirmation.  Appendix C of the Reference Manual also state:  "All registers are accessible with 32-bit accesses. The EPU registers are configurable via DCSR."

Regards,

Frank

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frank_o
Contributor III

Following your reply I had to take few steps back. 

The register is Big Endian but the RCW/PBI compiler seems to handle this.  So the code I have provided above does work.  The tool I was using to read back the values in Linux the problem.

Best regards

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ufedor
NXP Employee
NXP Employee

Correct memory map for the EPU is:

EPU.jpg

The QorIQ LS1043A Reference Manual will be fixed in the next revision.

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frank_o
Contributor III

Thank you for your reply.

So the information in Reference Manual Rev 5 were ok, and we should be able to access EPEVTCR0 register at address 0x20000050.  

But then we still have a problem.  Our original SW was programming this register with value 0x00000001 with PBI commands as follow:

//.pbi
// Setting EPU module, Base address 0x20000000
write 0x570158, 0x00002000
// Software must wait after updating the ALTCBAR.
// Below is the PBL Wait command (0xc0)
write 0x6100c0, 0x000fffff
awrite 0x000050, 0x00000001 // EVT0
awrite 0x000054, 0x00000001 // EVT1
awrite 0x000058, 0x00000001 // EVT2
awrite 0x00005C, 0x00000001 // EVT3
awrite 0x000060, 0x00000001 // EVT4
awrite 0x000074, 0x00000001 // EVT9
.end

But when we try to read back these registers in u-boot or Linux, their value are still 0.  Is there a way to confirm that the write was properly handled ?

Regards,

Frank

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ufedor
NXP Employee
NXP Employee

It could be an endian issue - please try:

awrite 0x000050, 0x01000000 // EVT0

....

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1,608 Views
frank_o
Contributor III

Following your reply I had to take few steps back. 

The register is Big Endian but the RCW/PBI compiler seems to handle this.  So the code I have provided above does work.  The tool I was using to read back the values in Linux the problem.

Best regards

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