LS1043A, Booting Process

[logeshs]

Hi,

In LS1043A, Kindly confirm my understanding in booting process. I had gone through the chapter 4 of the Reference Manual just want to confirm my understanding. Below i'm listing down in steps.

1. Processor should be powered up as per power up sequence with PORESETn in LOW state.

2. PORESETn is released from out of reset, with POR configurations pins are sampled.

3. only PORESETn will be out of reset and HRESET continues to be in RESET and RCW data is loaded from External memory during this time from RCW source. (Please confirm does this state is mentioned PBL?)

4. HRESET will be out of RESET and PBI takes place from PBI Source, i.e., If NOR is Chosen as PBI SRC then boot image is loaded from NOR and once booting is done it will go to linux page.

Please correct me if my understanding is wrong.

Thanks.

[alexander_yakov]

1. Yes, PORESET must be driven asserted at power-up sequence.

The following is said in LS1043A device datasheet, Section 3.2 "Power sequencing":

PORESET_B input must be driven asserted and held during this step.

2.PORESET must be asserted for at least 1 ms after VDD becomes stable.

This is said in LS1043A device datasheet, Table 27.

3. PBL is "Pre-Boot Loader", a system block which is described in section 1.4.4 of Reference Manual. This block may is used also to load RCW, but main purpose of this block is to load data for PBI process performed a bit later. Please see LS1043A Reference Manual, Section 4.4.1 "Power-on reset sequence" for details.

4. No, PBI and booting are two different processes. PBI means "Pre-Boot initialization", this process is used to pre-initialize several device registers before releasing core from reset and allowing core to boot. Booting is performed from reset vector, please see Section 11.3.34 of Reference Manual for details.

Both mentioned document can be obtained from LS1043A product page, "Documentation" tab:

QorIQ® Layerscape 1043A|NXP 

Have a great day,
Alexander
TIC

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[lgx]

Booting is performed from reset vector
Does it means that, PBI will update reset vector register using BOOTLOC, after core0 is released, core0 will boot from reset vector ?