Yes, LS1043A Device Datasheet also states this pin is reset configuration pin (see Table 1, reference to note 4).
However, there is no information about this pin in Reference Manual, Section "4.4.5 Power-on reset configuration".
This means this configuration pin is reserved for further use, please do not drive this pin externally at reset.
The following is said in LS1043A Design Checklist (application note AN5012):
This pin is a reset configuration pin. It has a weak (~20 kΩ) internal
pull-up P-FET that is enabled only when the processor is in its reset
state. This pull-up is designed such that it can be over powered by an
external 4.7 kΩ resistor. However, if the signal is intended to be high
after reset, and if there is any device on the net that might pull down
the value of the net at reset, a pull-up or active driver is needed.
This document is available for download from the LS1043A documentation page:
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