LPUART Rx using EDMA on LS1021A

[murali417]

Hi,

I am trying to enable data transfer from LPUART FIFO buffers to a RAM buffer using EDMA. My ideal case is to achieve this with out interrupting the processor in the whole process. But with the current setup configuration (specified below) I am not able to trigger the DMA. I really appreciate if anyone could take a look at it and see if I am missing any pieces of the puzzle.

DMA MUX:

DMAMUX2_CHCFG2 - 0xA0 - Enable and source as LPUART RX1

EDMA Setup:

DMA_CR - 0x0000040C - Enable round robin group and channel arbitration

DMA_ERQ - First tried with 0x0004_0000 and then 0xFFFF_FFFF

TCD : - for 18 - Base address - 0x02C0_1240

Source Address - 0x0295_000C - LPUART RX 1 Data Register address

SOFF - 0x0 - Since we do not want to change source address after copy is done

ATTR - 0x0202 - 4bytes

NBYTES - 4

SLAST - 0

DADDR - RAM buffer address

DOFF - 4

CITER - 1

BITER - 1

DLASTSGA - 0

CSR - 0

LPUART Setup: Using LPUART1 RX

LPUART1_BAUD - 0x0F20_4036

LPUART1_CTRL - 0x002C_0000

LPUART1_FIFO -  0x0000_0088

LPUART1_WATER - 0x0001_0003

I am guessing that LPUART is not initiating/generating the DMA request when Rx Water level mark is reached.

Thanks,

Murali

[alexander_yakov]

Sorry for delayed response

I do not see anything incorrect in your register settings except LPUART1_FIFO

For the value "LPUART1_FIFO =  0x0000_0088" - if this is a read-back value, than this means FIFO size is only one dataword. In this case setting watermark to 1 is incorrect, LS1021A Reference Manual says:

Receive Watermark
When the number of datawords in the receive FIFO/buffer is greater than the value in this register field, an
interrupt or a DMA request is generated. For proper operation, the value in RXWATER must be set to be
less than the receive FIFO/buffer size as indicated by FIFO[RXFIFOSIZE] and FIFO[RXFE] and must be
greater than 0.

For further debugging please:

1. reconfigure DMAMUX2_CHCFG2 to always-on slot to check if everything is correct with DMA configuration.

2. verify that LPUART reception works and generates interrupt on watermark 

Have a great day,
Alexander
TIC

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