Inter byte SPI delay

cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 

Inter byte SPI delay

1,761 Views
jbonhomme
Contributor I

Hello,

I have a custom board with LS1028A and a MCP2518FD CAN controller on SPI1 bus. All works fine but when we take a look at SPI bus, we see that performance are not maximum.

A SPI transfer is composed as following : many bytes are send and during all this time, CS is asserted. After, CS is released during a period (about 20us) and at the end of this time, another transfer begins with many byte send (always with CS tied low during transfer). This sequence is repeated 4/5 times.

We observe that :

- there are long inter byte delay (about 4us). A SPI byte takes about 0,7us. 

TEK00004.PNG

 

- there are long inter frame delay (about 20us). It corresponds to desasserted time of CS between 2 frames.

TEK00005.PNG

Settings of Tasc and Tcsc are good, and are correctly defied in device tree.  

If I understand datasheet, asserted CS during many bytes transfer correspond to continous mode operation. In this case inter byte delay shoud be sum of Tasc and Tcsc, but it is not true here.

We tried to set PDT and DT to reduce CS desasserted time without success. 

We tried to activate fast continuous mode to supress Tasc and Tcsc between byte without success. 

 

We didn't understand why all our registers modification haven't effect on SPI timing, and why we have these timings.

Has anybody have already this problem ? how to fix it ?

Regards

Jeremy

0 Kudos
2 Replies

1,298 Views
QorIQ-46
Contributor I

Hello Jbonhomme,

Did you finally solved your inter byte delay problem?

We're working with a LS1046A and notice similar behaviour during SPI transfers: 2µs delay between consecutive bytes (and 11µs between deassertion and reassertion of CS). We would like to reduce as much as possible the inter byte delay.

 @Pavel / @NXP: Is there any driver improvement planned in the coming future?

Any suggestion is welcome.

Thanks

0 Kudos

1,710 Views
Pavel
NXP Employee
NXP Employee

Linux BSP dSPI driver was not optimized for performance.

Check the CTARx[DT] value.

Check the CTAREx[DTCP] value.

Send multiple data frames using a single command frame. See the Section 30.5 in the LS1028a Reference Manual.

https://www.nxp.com/webapp/Download?colCode=LS1028ARM

 

See also the Section 30.6.

 

0 Kudos