Hello,
I have a custom board with LS1028A and a MCP2518FD CAN controller on SPI1 bus. All works fine but when we take a look at SPI bus, we see that performance are not maximum.
A SPI transfer is composed as following : many bytes are send and during all this time, CS is asserted. After, CS is released during a period (about 20us) and at the end of this time, another transfer begins with many byte send (always with CS tied low during transfer). This sequence is repeated 4/5 times.
We observe that :
- there are long inter byte delay (about 4us). A SPI byte takes about 0,7us.
- there are long inter frame delay (about 20us). It corresponds to desasserted time of CS between 2 frames.
Settings of Tasc and Tcsc are good, and are correctly defied in device tree.
If I understand datasheet, asserted CS during many bytes transfer correspond to continous mode operation. In this case inter byte delay shoud be sum of Tasc and Tcsc, but it is not true here.
We tried to set PDT and DT to reduce CS desasserted time without success.
We tried to activate fast continuous mode to supress Tasc and Tcsc between byte without success.
We didn't understand why all our registers modification haven't effect on SPI timing, and why we have these timings.
Has anybody have already this problem ? how to fix it ?
Regards
Jeremy
