ISI exception

cancel
Showing results for 
Search instead for 
Did you mean: 

ISI exception

629 Views
hv
Contributor II

I'm at a loss as to why a section of code raises an ISI exception even though the TLB has been mapped with an UX permission.  I would appreciate any ideas/suggestions as to what I could be missing.  Thanks!

0 Kudos
3 Replies

491 Views
alexander_yakov
NXP Employee
NXP Employee

Have you checked twice SRR0, SRR1 and MSR register contents, when the exception is taken?

0 Kudos

491 Views
hv
Contributor II

The ISI exception goes away when I set the SR bit (supervisor read) to 1. Why would that be?

0 Kudos

491 Views
hv
Contributor II

I checked them. The SRR0 points to a thread running in a memory section that was mapped with Memory coherence required, UX and UR bits are set to 1. SRR1 is shown to be 0x0000F902 (PR bit is set).

That’s why I didn’t understand why an ISI exception happened.

0 Kudos