How to partition the L3 Cacahe of P4080 using CodeWarrior?

[peterzheng]

Hi

Currently I was trying to partition the L3 cache (CPC) of P4080DS. Specifically to partition the L3 cache equally to the 8 parts to be used by each core available in the P4080DS, I

was told that this could be realized using CodeWarrior.

In this case, could you suggest how can I partition the L3 cache equally for  each of the core in QorIQ P4080DS by editing the file in CodeWarrior and

run some simple program?

Regards,

Peter Zheng,

[lunminliang]

Hi,

After looking through all your question, I can preliminarily know what you would like to do. Let me summarize from the platform point of view:

First, the CPC L3 Cache or part of CPC could not be designated for any core, it's platform shared resource.

Second, the way for this is using different physical address range.

To be specific, use different partition control registers and LAW for each part of address range for this purpose.

Please refer to Section 8.3.1.2 Partitioning Control Registers and Section 2.4 Local Access Window.

For example, for two cores core A and core B:

Core A will access DDR part A, core B will access DDR part B;

Core A use CPCPIRa/CPCPARa/CPCPWRa and LAWa, core B use CPCPIRb/CPCPARb/CPCPWRb and LAWb

LAWa is for DDR part A, LAWb is for DDR part B.

In LAWa, the CSD_ID equals the PID bit set in CPCPIRa, assume it's PIDa, the CPCPARa allow this type of transaction to be allocated in one of the ways defined in CPCPWRa, in CPCPWRa, you give four ways a0,a1,a2,a3 for example, lets say it's CPC part A.

Similarly setting those in LAWb. You need to give different PID, for example PIDb, and different ways b0, b1,b2,b3, lets say it's CPC part B.

Thus when cache miss happens on Core A, as it's accessing DDR part A, it will find in the 16 triples of partition control registers and find a match CSD_ID/PID in CPCPIRa, then allocate CPC part A with replacement algorithm. You need to make sure Core A only access DDR part A, if it access DDR part B, as registers CPCPIRb/CPCPARb/CPCPWRb and LAWb are also visible to Core A for those are all device level, it will find match CSD_ID/PID, and resulting in allocation in CPC B as well. That's why you could not make any part of CPC as private to any core.

It's a little complicated. Fortunately as Scott have suggested in your other thread you can do that in hv config tree

How does the L3 cache mapping to memory in P4080DS, how the address was translated?

Also you can do this in CodeWarrior by yourself. I hope I have made the description as clear as possible I could.

Have a great day,
Lunmin

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[peterzheng]

Hi Lunmin,

Thank you for your help, I have tried to implement the partitioning of CPC follow your suggestion. But there are some problems there. I have put in a new post. Can you help take a look?

Configure Initialization Script for P4080DS in CodeWarrior for CPC Partitioning

Thank you very much.

Regards,

Peter

[peterzheng]

Hi Lunmin,

Thank you for your detailed explanation. I think it is on the right track. Just want to clarify a few points.

(1) To configure those LAW and CPC registers, should I assign value to them by modifying the initialization file in this location workspace/project/CFG/P4080DS_init_core_cacheon.tcl in CodeWarrior?

(2) If I want to make sure that Core A only access DDR part A in your example, let's say, DDR part A has address range from 0x00000000 to 0x10000000, how do I write the code in C to make Core A 's program only access this part of DDR? Can you give me one example?

Thanks & Regards,

Peter Zheng