DDR4 write-leveling capabilities

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DDR4 write-leveling capabilities

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bfox
Contributor I

How much Clock-Strobe skew can the DDR4 capable T1024 Processors compensate for during write-leveling? A general PCB guideline is to wire the clock as long the strobe, however can the QorIQ DDR4 controllers maintain tDQSS requirements if the clock is shorter than the corresponding strobes and by how much?

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lunminliang
NXP Employee
NXP Employee

Please follow this item:

In fly-by topology, for a given byte lane, the clock trace length must be at least as long as the strobe trace length. In the case that the clock trace length is shorter, the following limits must be observed:

• For MPC8572 and MPC8536 only, the clock trace length must be longer or equal to the strobe trace length for a given byte lane.

• For all other devices, the clock trace length can be a maximum of 3.0 inches shorter than the strobe trance length for a given byte lane.

The Application note is available at:

https://www.freescale.com/webapp/Download?colCode=AN3940&location=null&Parent_nodeId=&Parent_pageTyp...

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lunminliang
NXP Employee
NXP Employee

Hi,

There are table about DDR4 and DDR3L SDRAM interface output AC timing specifications, in the hardware specification, cut some as below for reference.

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4. Note that tDDKHMH follows the symbol conventions described in note 1. For example, tDDKHMH describes the DDR timing(DD) from the rising edge of the MCK[n] clock (KH) until the MDQS signal is valid (MH). tDDKHMH can be modified through control of the MDQS override bits (called WR_DATA_DELAY) in the TIMING_CFG_2 register. This is typically set to the same delay as in DDR_SDRAM_CLK_CNTL[CLK_ADJUST]. The timing parameters listed in the table assume that these two parameters have been set to the same adjustment value. See the chip reference manual for a description and explanation of the timing modifications enabled by the use of these bits.

7. Note that it is required to program the start value of the MDQS adjust for write leveling.

As experience I think it's better not to route CK shorter than DQS. For DDR4, the guidelines provide in AN3940 could be followed.

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