DDR4 ECC error injection on LX2080A

[RoseWen]

Hi,

I want to ensure the ECC functionality are proper on LX2080A.

In the LX2160A Reference Manual, the DDR memory controller will detect four different kinds of errors:

1) training 2) single-bit 3) multi-bit 4) memory select errors.

Now I generate single-bit errors and multi-bit errors as below steps: (Please refer to the attached test log)

Method1: Setting a mask bit causes the corresponding ECC bit to be inverted on memory bus writes.

    1.1 Check DDR_SDRAM_CFG[ECC_EN] is 1 (ECC enabled)

    1.2.a Set ECC_ERR_INJECT[EEIM] to 0x01 (inject 1 bit ECC parity errors) for single-bit errors

    (1.2.b Set ECC_ERR_INJECT[EEIM] to 0xff (inject 8 bits ECC parity errors) for multi-bit errors)

    1.3 Set ECC_ERR_INJECT[EIEN] to 1 (error injection enabled)

    1.4  Set ECC_ERR_INJECT[EIEN] to 0 (error injection disabled)

    1.5 Check ERROR_DETECT and ERR_SBE

Method2: Setting a bit causes the corresponding data path bit to be inverted on memory bus writes.

    2.1 Set ECC_ERR_INJECT[EIEN] to 1 (error injection enabled)

    2.2.a Set DATA_ERR_INJECT_LO to 0x01 (the LSbit of 64-bit word is going to be inverted) for single-bit errors

    (2.2.b Set DATA_ERR_INJECT_LO to 0x03 (the LSbit of 64-bit word is going to be inverted) for multi-bit errors)

    2.3 Set ECC_ERR_INJECT[EIEN] to 1 (error injection enabled)

    2.4 Check ERROR_DETECT and ERR_SBE

Questions:

Q1: Could you please help me to confirm above steps are correct or not?

Q2: How to automatically fix single-bit errors? (I have enable ECC_FIX_EN and set ECC_SCRUB_INT but it's no work.)

Q3: How to generate ecc error interrupt? (I have enable SBEE but no interrupt message on U-Boot)

Q4: How to verify the others errors like training and memory select errors?

Regards,

Rose

[SebastianG]

Hello @RoseWen,

Regarding to the question "Could you please help me to confirm above steps are correct or not?"

     ->The method 2 is the correct sequence for single bit and multiple bit error, We have found this information in our database that can be useful to this procedure:

1) DATA_ERR_INJECT_LO (0x1080E04) = 00000001 (the LSbit of 64-bit word is going to be inverted);

2) ERR_INJECT[EIEN]=1 (0x1080E08); enable injection

3) to write 0x0000000000000000 to some DDR location (actually 0x0000000000000001 will be written due to above steps);

4) repeat step 3 for a number of address locations to inject the number of single bit errors;

5) ERR_INJECT[EIEN]=0; disable injection

Reading of the location used in step 3 should result in value 0000000000000000 (LSbit is corrected). ERR_DETECT register should report a single-bit ECC error.

Regarding to the question "How to automatically fix single-bit errors? (I have enable ECC_FIX_EN and set ECC_SCRUB_INT but it's no work.)" and the question "How to generate ECC error interrupt? (I have enable SBEE but no interrupt message on U-Boot)"

    ->Could you please provide us with the DDR logs registers at the moment when you face this situation?

Regarding to the question "How to verify the others errors like training and memory select errors?"

    ->I will answer this question in our next conversation

Regards,

Sebastian

[RoseWen]

Hi Sebastian,

Regarding to the reply "The method2 is the correct sequence for single bit and multiple bit error, We have found this information in our database that can be useful to this procedure" 

-> In my last test log, I don't need to write data to some memory location, the ERR_DETECT already report single-bit ECC error. Only need to set step1,2 and 5 you provided.

-> In my last test log, the method1 will also report single-bit/multiple bit errors, is this process wrong?

Regarding to the last time question 2 and 3, please refer to the attached test log.

Thanks,

Rose

[RoseWen]

Hi,

Any updates?

Rose

[SebastianG]

hello @RoseWen,

This is an update from the Apps team:

----

The ECC in LX2080A is a SECDED, this means single bit error correction and double bit error detection. the single bit errors will increment the SBEC (single bit error counter) till it reaches the SBET(single bit error threshold). once the threshold is reached the ERR_DETECT register SBE flag will be set. you can detect the SBE either by checking the SBEC or the ERR_DETECT register.

The multi-bit errors, only guarantee any two bit flip detections, and ERR_DETECT MBE flag will be set. if you do more than two bit flip in your test, the ECC may or may not be able to detect it.

----

[RoseWen]

Hi

Why use the same reply to answer different questions?

This answer is not what I asked at all.

[SebastianG]

Apologies for the delayed response and thank you for the patience,

Could you please tell me the value that you set for ECC scrubbing interval?

[SebastianG]

Hello @RoseWen,

Apologies for the delayed response,

Just to let you know that I am working with the apps Team, I will let you know as soon as I have an update.

Thank you so much for your patience

[SebastianG]

Hello @RoseWen,

I would like to inform you that I'm working on your questions, I will let you know as soon as I have an update.

Thank you so much for your patience

Regards,

Sebastian