DDR3 multiple bit error in P1012

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DDR3 multiple bit error in P1012

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carlosterleirai
Contributor I

Hello,

I am using a P1012 and a DDR3 memory.

I am using write leveling.

The following documents are referenced in this question:

AN4039 Rev. 4, 11/2014

P1012RM Rev. 6, 01/2013

The uP shows multiple bit error in DDR3 ECC with the initial configuration (DDR_SDRAM_CLK_CNTL[CLK_ADJUST] = 1/4 and DDR_WRLVL_CNTL[WRLVL_START] = 1/8).

We have changed the initial configuration. Now the value of DDR_SDRAM_CLK_CNTL[CLK_ADJUST] is the same as DDR_WRLVL_CNTL[WRLVL_START] = 1/8,  it appears to work properly. It doesn't work with 0 or 1/4 values.

1) When a DDR3 multiple bit error is detected the uP stop working, even when interruptions are disabled. Is there any way to recover from this error?. I have seen that the only way is to disable error detection and correction.

2) Is DDR_WRLVL_CNTL[WRLVL_START] totally equivalent to DDR_TIMING_CFG_2[WR_DATA_DELAY]?

I´m asking this question to know if the following sentences also applies to DDR_WRLVL_CNTL[WRLVL_START]:

  2.1) AN4039/Table 8/WR_DATA_DELAY field - "The value selected for the write data delay should closely follow the DDR_SDRAM_CLOCK_CTRL [CLK_ADJUST] field value."

Also AN4039/Table 14/CLK_ADJUST field - "So, if WR_DATA_DELAY is not changed to match the CLK_ADJUST change, an offset is added between MCK and DQS."

So I suppose that the value for DDR_WRLVL_CNTL[WRLVL_START] shall be the same to DDR_SDRAM_CLK_CNTL[CLK_ADJUST].

  2.2) P1021RM/Section 8.4.7 DDR SDRAM timing configuration 2 (DDR_TIMING_CFG_2)/WR_DATA_DELAY field - "However, for WR_DATA_DELAY settings of 0 clocks and 1/4 clocks, the write preamble is driven low for the entire DRAM cycle. If the preamble needs to switch high first (to meet DDR3 specifications), then these values should not be used."

So I suppose that the values "0" and "1/4" shall not be used for DDR_WRLVL_CNTL[WRLVL_START] using DDR3 memories.

Thanks and regards

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r8070z
NXP TechSupport
NXP TechSupport

Have a great day,

1) When a DDR3 multiple bit error is detected the uP stop working, even when interruptions are disabled. Is there any way to recover from this error?. I have seen that the only way is to disable error detection and correction.

2) DDR_WRLVL_CNTL[WRLVL_START] is not totally equivalent to DDR_TIMING_CFG_2[WR_DATA_DELAY].
AN4039/Table 8 says “If write leveling is enabled (that is, DDR_WRLVL_CNTL[WRLVL_EN] =1) then WR_DATA_DELAY field is ignored by the memory controller.   For rare cases where write leveling is disabled (that is, DDR_WRLVL_CNTL[WRLVL_EN] = 0) then this field should be configured so that the first rising edge of MDQS (strobe) for a write operation meets the DRAM tDQSS specification. tDQSS is a JEDEC-defined timing parameter ensuring that, during a write operation, the controller issues the strobe no earlier than 75 percent, and no later than 125 percent, of the rising edge of the clock.”
When write leveling is enabled (that is, DDR_WRLVL_CNTL[WRLVL_EN] = 1) WRLVL_START defines the initial strobe position for the write levelling procedure. It has to be set so that the controller initially issues the strobe earlier than rising edge of the clock. In order to measure required delay during write levelling DRAM samples clock on the strobe. First the low level must be sampled then DDR3 controller increases strobe delay until high level is sampled.

 

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r8070z
NXP TechSupport
NXP TechSupport

Have a great day,

1) When a DDR3 multiple bit error is detected the uP stop working, even when interruptions are disabled. Is there any way to recover from this error?. I have seen that the only way is to disable error detection and correction.

2) DDR_WRLVL_CNTL[WRLVL_START] is not totally equivalent to DDR_TIMING_CFG_2[WR_DATA_DELAY].
AN4039/Table 8 says “If write leveling is enabled (that is, DDR_WRLVL_CNTL[WRLVL_EN] =1) then WR_DATA_DELAY field is ignored by the memory controller.   For rare cases where write leveling is disabled (that is, DDR_WRLVL_CNTL[WRLVL_EN] = 0) then this field should be configured so that the first rising edge of MDQS (strobe) for a write operation meets the DRAM tDQSS specification. tDQSS is a JEDEC-defined timing parameter ensuring that, during a write operation, the controller issues the strobe no earlier than 75 percent, and no later than 125 percent, of the rising edge of the clock.”
When write leveling is enabled (that is, DDR_WRLVL_CNTL[WRLVL_EN] = 1) WRLVL_START defines the initial strobe position for the write levelling procedure. It has to be set so that the controller initially issues the strobe earlier than rising edge of the clock. In order to measure required delay during write levelling DRAM samples clock on the strobe. First the low level must be sampled then DDR3 controller increases strobe delay until high level is sampled.

 

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Note: If this post answers your question, please click the Correct Answer button. Thank you!
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carlosterleirai
Contributor I

Hello Serguei,

 

Thanks for the reply.

 

Please tell me if I'm wrong.

 

I have understood that the strobe signal should occur earlier than the clock. So please, imagine a perfect routed system, where CLK_ADJUST is set to 1/2 to have the edge at the center of the steady state of the address/command/control signals. The WRLVL_START value for this system should be less than 1/2, that is 3/8 or 1/4?

 

Thanks and regards

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r8070z
NXP TechSupport
NXP TechSupport

The WRLVL_START value is required for write levelling in case of fly-by layout. It depends from clock and strobe  times of flight (ToF).  It is supposed that clock ToF is greater than strobe ToF for all chips in the chain. So in this case for CLK_ADJUST=1/2 suitable WRLVL_START is 1/4 or 1/2. See AN4039 for the recommended adjusting of the WRLVL_STAR value.

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carlosterleirai
Contributor I

Thank you for all Serguei.

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