DDR3 Clock Termination!

[qammarabbas]

Hi,

I am trying to interface T1042 with DDR3 memory chips in fly by toopology. The DDR3 designer checklist (AN3940) suggests that the differential clock pairs should have a differential termination on the memory side. Why is that necessary?
Moreover, my simulation results on Hyperlynx show better clock waveform when there is no differential termination. I have just used the VTT termination.

[Bulat]

Hello,

looking at the AN3940 I can not find where it suggests that "the differential clock pairs should have a differential termination on the processor side". Can you navigate me?

Regards,

Bulat

[qammarabbas]

Sorry, it's the memory side. Query updated. Please see point 30.

[Bulat]

Point 30 relates to DQS signals, i.e. does not relate to your original question at all.

Yes, parallel termination of the signals should be placed at the end of lines, on the memory side in case of clocks.

Note that the AN3940 suggests following: "Different termination techniques may also prove valid and useful, but are left to the designer to validate through simulation." So it's up to you and your simulations how to build the termination in better way. You may also want to simulate clock termination scheme that JEDEC recommends for DDR3 DIMMs. That one is used on all existing DIMMs.

Regards,

Bulat