DDR initialization failed: Invalid value at 0xF4: 0x0003102

[athershehzad]

I am trying to validate my DDR settings using code warrior validation tool. First it was giving me error D_INIT was not cleared by hardware but I manually cleared the D_INIT bit. Now it is giving me this error "DDR initialization failed: Invalid value at 0xF4: 0x0003102" How can I solve this issue ? And what is this address ?

Regards,

Ather

[KLN]

Hi ufedor /athershehzad

We are also facing the same issue with DDR with T2080: 

Exception: (<<Error configuring the target! - DDR initialization failed: D_INIT was not cleared by hardware!>>)

Link: https://community.nxp.com/t5/CodeWarrior-for-QorIQ/T2080-DDR-Validation-Error-D-INIT-failed/m-p/1727...

Can you tell what you've done to resolve this?

It seems to be this Issue is been faced by many times and there is no proper documentation regarding this issue!!!!

It is better to properly document this issue on how to resolve and what to be taken care!!

[ufedor]

You wrote:

> I manually cleared the D_INIT bit.

What exactly you have done?

What was and is DDR_ERR_DETECT value?

Please understand that inability to complete initialization (D_INIT=1) means that DDR controller is unable to operate properly.

[athershehzad]

What exactly you have done?

I had cleared DRAM Data Initialization bit in DDR_sdram_Config_2 register.

What was and is DDR_ERR_DETECT value?

Both times ERR_DETECT contains 0x00000080. 

You can also see snapshots as an attachment

Regards,

Ather

[ufedor]

3) Which processor is in question?

4) Please provide the DDR connection schematics as searchable PDF for inspection.

Possible causes for the DDR_ERR_DETECT[ACE] being set:
1) DDR read data path calibration error
2) MDICx signals are not properly terminated
3) Write leveling calibration unsuccessful completion

There are two possible root causes of ACE bit set:
- Register setting is not optimized
- There is a HW issue

It is recommended to doublecheck:
a) DDR connection referring the AN3940 - Hardware and Layout Design Considerations for DDR3 SDRAM
b) DDR controller settings referring the AN4039 - PowerQUICC and QorIQ DDR3 settings
c) DDR powering and noise level amplitude at the AVDD_DDR
d) DDR MCK frequency

e) reset to DDR SDRAM is applied as described in the AN5097 - Hardware and Layout Design Considerations for DDR4 SDRAM, Appendix B DRAM reset signal considerations

[athershehzad]

3) Which processor is in question?

T1042

4) Please provide the DDR connection schematics as searchable PDF for inspection.

Please find in the attachment

1) DDR read data path calibration error

How to check this error

2) MDICx signals are not properly terminated

Please verify from schematics

3) Write leveling calibration unsuccessful completion

Yes. that what the code warrior tool is telling us.

- Register setting is not optimized

Is there any any forum from where I can get the optimized settings for my controller?

[ufedor]

Please create a Technical Case:

1)    open www.nxp.com
2)    Select "Support" -> "All Support Options"
3)    Click "Go to Tickets"
4)    Log in with your NXP login and password
5)    On the "Group, Create and View your support cases" page press "+ Add a new case" to start the process.