DDR_MCKE Signal Descriptipon

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DDR_MCKE Signal Descriptipon

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Contributor II

Hi!

I am designing a custom board using T1042 and I am using on board discrete DDR3 RAM chips. I am following the design T1042RDBA reference design board. It is using DDR3 connector but I want to use onboard chips.

While following the design I came across with the signals i.e. MCKE0, MCKE1. These signals are output of the processor and input of the RAM chips But in reference design, they are also driven by CPLD through MOSFET. What is the reason for that ? Isn't it a problem that an output pin is being driven by CPLD?However, in the pin description table, note is written for the pins that During reset, these pins are actively driven. 

My confusion is that what is the purpose of driving these pins through CPLD?

Regards,

Ather

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NXP TechSupport
NXP TechSupport

You wrote:
> what is the purpose of driving these pins through CPLD?
CPLD function for the CKE_ISO_EN signal is:

    assign    cke_iso_en = ~evt_brd_iso;

where evt_brd_iso internal signal corresponds to EVT_BRD_ISO (IRQ_OUT_B).

The IRQ_OUT_B has multiplexed function EVT_B[9] which is used to enable isolation on the board during deep sleep when MCKE signals are not driven and will float.  

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