I am designing a custom board using T1042 and I am using on board discrete DDR3 RAM chips. I am following the design T1042RDBA reference design board. It is using DDR3 connector but I want to use onboard chips.
While following the design I came across with the signals i.e. MCKE0, MCKE1. These signals are output of the processor and input of the RAM chips But in reference design, they are also driven by CPLD through MOSFET. What is the reason for that ? Isn't it a problem that an output pin is being driven by CPLD?However, in the pin description table, note is written for the pins that During reset, these pins are actively driven.
My confusion is that what is the purpose of driving these pins through CPLD?