You need to modify DDR timing configuration in ATF source code for your custom board.
In your Yocto build environment, please run the following command to fetch atf source code.
1. $ bitbake atf -c cleansstate
2. $ bitbake atf -c patch
3. Go to atf source code folder build_ls1046ardb/tmp/work/ls1046ardb-fsl-linux/atf/git-r0/git, please modify plat/nxp/soc-ls1046/ls1046ardb/ddr_init.c according to your target board.
If there is SPD on your target board, please modify the following section.
static const struct rc_timing rce[] = {
{1600, 8, 7},
{1867, 8, 7},
{2134, 8, 9},
{}
};
static const struct board_timing udimm[] = {
{0x04, rce, 0x01020304, 0x06070805},
};
If there is no SPD on your custom board, please define CONFIG_STATIC_DDR in plat/nxp/soc-ls1046/ls1046ardb/platform_def.h, and modify static_2100, static_1800 or static_1600 according to your target board.
4. Rebuild atf
$ bitbake atf -c configure -f
5. $ bitbake atf
6. Go to step 3 to continue to do modification.
According to your description, you have working u-boot on the target board, you could use CodeWarrior to connect to the target board to read DDR configuration parameters from the target board. In CodeWarrior IDE, please create a QCVS project with "reading from target" method, then get DDR configuration parameters in ddr_init1.c in Generated_Code folder.
