Aborting partial CPU Power-Up

[nikhilrao]

We intend to follow the attached power sequence for the LS1021A CPU.  We are also utilising a MC34VR500V1ES PMIC in our design.

Page 58 of the LS1021A Datasheet (Rev 4, 11/2016), states that "All supplies must be at their stable values within 400ms."    In normal situations with a working board, we will be able to meet this 400ms requirement with a good margin.

But in the event of a failure of the MC34VR500 PMIC, we could have the 3.3V rail (which powers BVDD, D1VDD, DVDD, L1VDD, LVDD, EVDD, USB_HVDD) active for 200 to 300ms before we shut it down with our CPLD.  Would this partial power up (i.e. only powering 3.3V rail) and aborting it within 300ms cause any damage to the LS1021A CPU?

Note we are using a CPLD which is different from the one used in the TWR and IoT boards, as we do not require it to carry out as many functions.

[Pavel]

The LS1021a does not have special requirement for power down sequence. There is only requirement that the power-down cycle must complete such that power supply values are below 0.4 V before a new power-up cycle can be started.

See also the Table 2 of the LS1021a Datasheet. Notes to this Table requires that xVin voltage should be below then xVdd+0,3.

Have a great day,
Pavel Chubakov

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[nikhilrao]

Thank you Pavel. This answers my query.