UBOOT from eSPI for B4860

[shermie]

We have a B4860 on a custom board and due to HW issues with NOR we are trying to boot from SPI, however I am not having much luck and some bits don't quite add up.

I understand the PBI setting up the Complex memory to be SRAM and mapping it to 0xFFF8_0000 to 0xFFFF_FFFF (512KB)

I don't know what the following section does

#Configure alternate space

09000010 00000000

09000014 ff000000

09000018 81000000

I presume the last PBI Flush PBL command copies the rest of the data (i.e. UBOOT) to SRAM

However when I compile UBOOT (using the SDK - I created the entry to add SPI build) the UBOOT image is 768 KB and the B4860_SPIFLASH.conf has SYS_TEXT_BASE set to 0xFFF4_0000 so outside of the SRAM area.  If I try and change the SYS_TEXT_BASE to 0xFFF8_0000 the compile fails as everything has to move location as it doesn't fit.

So my question is how does this ever work?  Am I missing something (I have no doubt I am)?

Would it work to setup both CPC memory to SRAM interlaced and then map in the area?

For some reason CW (10.5.1) doesn't contain the tcl and MEM files for debugging from SPI\CPC but will try and create them by looking at others.

Any help or indication/pointing in the right direction would be great

Thanks

Paul

[Pavel]

Find the following on the SDK information centre: eSPI/SD/NAND Boot.

Look at the following page:

https://freescale.sdlproducts.com/LiveContent/content/en-US/QorIQ_SDK/GUID-CF227019-184C-466E-AA63-E...

Find the following on this page:

Note: for T4240/T2080(with 512KB CPC) and T1024/T1040(with 256KB CPC), CPC are not big enough to store the U-boot since the U-boot size is 768KB, a two-stage boot is introduced which produces two U-boot images, the first stage u-boot is loaded to CPC, and run in CPC, which will init DDR and load the second stage u-boot to DDR, then jump to DDR to boot up to U-boot command line.

See u-boot documentation for SPL generation:

https://android.googlesource.com/device/ti/bootloader/uboot/+/master/doc/README.SPL

See also the following page:

https://community.nxp.com/thread/352188

Look at also the following pages;

https://freescale.sdlproducts.com/LiveContent/content/en-US/CodeWarrior_PA_Knowledge_Center/GUID-416...

https://freescale.sdlproducts.com/LiveContent/content/en-US/CodeWarrior_PA_Knowledge_Center/GUID-C00...

See also attached file.

Have a great day,
Pavel Chubakov

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[shermie]

Hi Pavel

Thanks for the response, that now makes more sense.

Paul