Dear Bulat,
Please find the header file for DDR below:
/*
* DDR Setup
*/
#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
#define CONFIG_SYS_DDRCDR 0x62000002
#undef CONFIG_SPD_EEPROM
#if defined(CONFIG_SPD_EEPROM)
/* Determine DDR configuration from I2C interface
*/
#define SPD_EEPROM_ADDRESS 0x51 /* DDR SODIMM */
#else
/* Manually set up DDR parameters
*/
/*#define CONFIG_SYS_DDR_SIZE 64 */ /* MB */
#define CONFIG_SYS_DDR_SIZE 256 /* MB */
/* #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
| CSCONFIG_ROW_BIT_13 \
| CSCONFIG_COL_BIT_9) */
/* 0x80010101 */
//#define CONFIG_SYS_DDR_CS0_CONFIG 0x80840102
#define CONFIG_SYS_DDR_CS0_CONFIG 0x80844102
#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
| (0 << TIMING_CFG0_WRT_SHIFT) \
| (0 << TIMING_CFG0_RRT_SHIFT) \
| (0 << TIMING_CFG0_WWT_SHIFT) \
| (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
| (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
/* 0x00220802 */
/*#define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
| (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
| (2 << TIMING_CFG1_ACTTORW_SHIFT) \
| (5 << TIMING_CFG1_CASLAT_SHIFT) \
| (3 << TIMING_CFG1_REFREC_SHIFT) \
| (2 << TIMING_CFG1_WRREC_SHIFT) \
| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
| (2 << TIMING_CFG1_WRTORD_SHIFT)) */
/* 0x26253222 */
//#define CONFIG_SYS_DDR_TIMING_1 0x3935d342
#define CONFIG_SYS_DDR_TIMING_1 0x26256222
#define CONFIG_SYS_DDR_TIMING_2 0x0f9028c7
/*
#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
| (31 << TIMING_CFG2_CPO_SHIFT) \
| (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
| (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
| (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
| (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
| (7 << TIMING_CFG2_FOUR_ACT_SHIFT)) */
/* 0x1f9048c7 */
#define CONFIG_SYS_DDR_TIMING_3 0x00000000
#define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
/* 0x02000000 */
/*#define CONFIG_SYS_DDR_MODE ((0x4448 << SDRAM_MODE_ESD_SHIFT) \ */
#define CONFIG_SYS_DDR_MODE ((0x4440 << SDRAM_MODE_ESD_SHIFT) \
| (0x0232 << SDRAM_MODE_SD_SHIFT))
/* 0x44480232 */
#define CONFIG_SYS_DDR_MODE2 0x8000c000
/* #define CONFIG_SYS_DDR_INTERVAL ((800 << SDRAM_INTERVAL_REFINT_SHIFT) \ */
#define CONFIG_SYS_DDR_INTERVAL ((0x00c8 << SDRAM_INTERVAL_REFINT_SHIFT) \
| (0x0064 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
/* 0x03200064 */
/*#define CONFIG_SYS_DDR_CS0_BNDS 0x00000003 */
//#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F
#define CONFIG_SYS_DDR_SDRAM_CFG 0x43080000
/*#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
| SDRAM_CFG_SDRAM_TYPE_DDR2 \
| SDRAM_CFG_32_BE) */
/* 0x43080000 */
#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
#endif
/*
* Memory test
*/
#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
#define CONFIG_SYS_MEMTEST_START 0x00030000 /* memtest region */
//#define CONFIG_SYS_MEMTEST_END 0x03f00000
#define CONFIG_SYS_MEMTEST_END 0x07f00000
/*
* The reserved memory
*/
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#define CONFIG_SYS_RAMBOOT
#else
#undef CONFIG_SYS_RAMBOOT
#endif
/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
//#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 384 kB for Mon */
#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
/*
* Initial RAM Base Address Setup
*/
#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
#define CONFIG_SYS_GBL_DATA_OFFSET \
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
/*
* Local Bus Configuration & Clock Setup
*/
#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
#define CONFIG_SYS_LBC_LBCR 0x00000000
/*
* FLASH on the Local Bus
*/
#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
//#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE /* FLASH base address */
//#define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size is 16M */
#define CONFIG_SYS_FLASH_SIZE 64 /* FLASH size is 16M */
//#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
/* Window base at flash base */
#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
//#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB)
#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000019
#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
| BR_PS_16 /* 16 bit port */ \
| BR_V) /* valid */
#define CONFIG_SYS_OR0_PRELIM 0xFC000FF7
/*#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
| OR_GPCM_XAM \
| OR_GPCM_CSNT \
| OR_GPCM_ACS_DIV2 \
| OR_GPCM_XACS \
| OR_GPCM_SCY_15 \
| OR_GPCM_TRLX_SET \
| OR_GPCM_EHTR_SET \
| OR_GPCM_EAD) */
/* 0xFE006FF7 */
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
//#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
#undef CONFIG_SYS_FLASH_CHECKSUM
/* Second Flash */
#define CONFIG_FLASH1_BASE 0x88000000
#define CONFIG_LBLAWBAR1_PRELIM CONFIG_FLASH1_BASE
#define CONFIG_LBLAWAR1_PRELIM 0x80000019 /*LBLAWAR2 - enable, size = 64MB */
#define CONFIG_SYS_BR1_PRELIM (CONFIG_FLASH1_BASE | /* Flash Base address */ \
(2 << BR_PS_SHIFT) | /* 16 bit port size */ \
BR_V) /* valid */
#define CONFIG_SYS_OR1_PRELIM 0xFC000FF7 /* Mask for 64MB Flash size */
/*
* Memory map for DS0 Cross Connect
*/
#define CONFIG_SYS_LBLAWBAR2_PRELIM 0xFC000000
#define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000010 /*LBLAWAR2 - enable, size = 128KB*/
//#define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000011 /*LBLAWAR2 - enable, size = 256KB*/
#define CONFIG_SYS_BR2_PRELIM 0xFC001001 /* BR2 base address at 0xFA008000, port size 16 bit, */
#define CONFIG_SYS_OR2_PRELIM 0xFFFE0FF7 /* OR2 128KB size */
//#define CONFIG_SYS_OR2_PRELIM 0xFFFC0FF7 /* OR2 256KB size */
Please find the DDR section:
