Booting P1010 from SPI

[tsybezoff]

Hi to all!

We used the P1010 (part number P1010NSN5HHA) with DDR 667MHz (MT41K256M16 - 4Gb) configuration , SPI boot and a non-trusted system mode. Now we use P1010 chip (part number P1010NXE5KHB), and our embedded system (baremetal) is not working. After power-on reset we have loading from SPI flash in ROM mode, but CPU does not start (no code execution). When we use the debugger CodeWarrior TAP (RAM mode), code executes normally.

What is the difference between chips by part number P1010NSN5HHA and P1010NXE5KHB?

How it affects system boot?

[tsybezoff]

Can we work in non-secure mode with P1010NXE5KHB?
We change chip P1010NSN5HHA for P1010NXE5KHB. As result our system doesn't work (in debug it works perfect). SPI booting is complete after reset on-chip, but CPU is not running.
What's the problem, guys???

[alexander_yakov]

Yes, the P1010NXE5KHB can work in non-secure mode. The fact that security block is available - should not prevent the device from booting, if boot code does not use this block. The fact that RAM mode works, but only ROM image does not work - does not mean that the problem is related to security block. 

Please run your ROM code under debugger control and determine, what exactly fails.

[tsybezoff]

We fixed the problem. In ROM init source we commented a row of source code at Tlb1Entries: 0x10030000, 0x80000100, 0xFF70000A, 0xFF700015 //# define 4KB   TLB1 entry 3: 0xFF700000 - 0xFF7FFFFF; for default CCSR Space (old)

Please, explain this part of TLB settings. We didn't find any info about that.

[alexander_yakov]

Partnumber decoding table from P1010 Hardware Specifications:

So, differences are: Ext temp range instead of Std, Encryption block present, higher maximum core frequency and another silicon revision. The difference between silicon revisions is in several silicon bugs fixed, please see device errata for details.

The software may fail to boot because of several reasons, for example because of different SVR/PVR value.

Have a great day,
Alexander
TIC

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

[tsybezoff]

Hi, Alex!

Please, give us a link to device errata for details!!!
You don't understand our question))) We want to know about differences in spi boot process (boot settings etc.) between P1010NSN5HHA and P1010NXE5KHB.

[tsybezoff]

We have no problem with P1010 rev.1. Code is not executing at P1010 rev.2, however our embedded scheme is not change.

[alexander_yakov]

P1010 device errata is currently "Preliminary, Confidential" and not available on our public site. Please contact your distributor to sign NDA and get this document.

There are no known bugs which may prevent rev.2 device from booting from SPI, if rev.1 works perfect. Please run your boot code under debugger control and determine, what exactly fails.

[tsybezoff]

Rev.2 work perfect in debug mode (RAM) . Problem only with ROM mode... Can SEC engine to affect at code execution??? 

P.S. we work in non-trusted system mode