Setting core affinity

[ankita_hegde]

Dear Team,

We are using iMX8DXL processor. Is there any way to make all the SPI related task to work in single core? Do let us know if there is any procedure or example to do so.

Regards,

Ankita

[Zhiming_Liu]

Hello,

To set the CPU affinity for the SPI interrupt to a specific core (e.g., CPU0):

echo 1 > /proc/irq/<spi_irq_number>/smp_affinity

Reference: https://docs.kernel.org/core-api/irq/irq-affinity.html

Best Regards,
Zhiming

[ankita_hegde]

Hi,
Is there any way we can set core affinity in driver code?

Regards,
Ankita

[Zhiming_Liu]

Hello,

To set it in driver, please use irq_set_affinity referring the drivers in kernel. For example, drivers/perf/fsl_imx9_ddr_perf.c

	ret = irq_set_affinity(pmu->irq, cpumask_of(pmu->cpu));
	if (ret) {
		dev_err(pmu->dev, "Failed to set interrupt affinity\n");
		goto ddr_perf_err;
	}

Best Regards,
Zhiming

[ankita_hegde]

Hi,
When we tried to use the first procedure for the below interrupt, we got an input/output error
204: 4820 0 gpio-mxc 12 Edge can3

echo 2 > /proc/irq/204/smp_affinity
-sh: echo: write error: Input/output error

Regards,
Ankita

[Zhiming_Liu]

Hello,

If you want to assign irq to the second core, please try.

echo 1 > /proc/irq/204/smp_affinity

Best Regards,
Zhiming

[ankita_hegde]

Hi,
Even with this, its the same error for this irq.

204: 4820 0 gpio-mxc 12 Edge can3

Regards,
Ankita

[Zhiming_Liu]

Hello,

The default gpio-mxc driver doesn't support affinity interfaces, you could refer below thread to add code in driver if you need.

https://community.nxp.com/t5/i-MX-Processors/i-MX7-IRQ-affinity-setting-for-GPIO-interrupts/m-p/7609...

Best Regards,
Zhiming

[ankita_hegde]

Hi,
Even by adding these driver changes, I am not able to change the affinity.
Regards,
ANkita

[Zhiming_Liu]

Hello,

The /proc/irq/xxx/smp_affinity can only work with those irqs binding to GICv3. For standard gpio driver, there is no such interfaces to handle smp_affinity. 

For the gpio smp affinity, the previous thread gave a special code in gpio driver to support bind one gpio band irq to one cpu core, you can add log print to verify these code, but you can't check if this can work in rootfs as this is not official way to support affinity feature in driver.

Best Regards,
Zhiming

[ankita_hegde]

Hi,

We have added the affinity related code in gpio-mxc driver for iMX8DXL with 5.15.52 BSP as below:

...
if (of_device_is_compatible(np, "fsl,imx21-gpio")) {
/*
* Setup one handler for all GPIO interrupts. Actually setting
* the handler is needed only once, but doing it for every port
* is more robust and easier.
*/
irq_set_chained_handler(port->irq, mx2_gpio_irq_handler);
+ irq_set_affinity_hint(port->irq, cpumask_of(2));
} else {
/* setup one handler for each entry */
irq_set_chained_handler_and_data(port->irq,
mx3_gpio_irq_handler, port);
+ if (port->irq_high > 0)
+ irq_set_affinity_hint(port->irq, cpumask_of(2));
if (port->irq_high > 0)
/* setup handler for GPIO 16 to 31 */
irq_set_chained_handler_and_data(port->irq_high,
mx3_gpio_irq_handler,
port);
+ irq_set_affinity_hint(port->irq_high, cpumask_of(2));
}
...

But when we do cat /proc/interrupts, we get the result as below, where the affinity is still in CPU 0

root@imx8dxl-iwg46s:~# cat /proc/interrupts
CPU0 CPU1
9: 0 0 GICv3 25 Level vgic
11: 3291 3729 GICv3 30 Level arch_timer
12: 0 0 GICv3 27 Level kvm guest vtimer
14: 0 0 GICv3 23 Level arm-pmu
15: 0 0 GICv3 372 Level imx_mu_chan[3-0]
16: 0 0 GICv3 374 Level imx_mu_chan[3-0]
17: 0 0 GICv3 376 Level imx_mu_chan[3-0]
18: 0 0 GICv3 380 Level imx_mu_chan[3-0]
19: 0 0 GICv3 382 Level imx_mu_chan[3-0]
21: 0 0 GICv3 350 Level imx_mu_chan[3-0]
22: 0 0 GICv3 351 Level imx_mu_chan[3-0]
23: 0 0 GICv3 352 Level imx_mu_chan[3-0]
50: 537 0 GICv3 260 Level fsl-lpuart
51: 0 0 GICv3 261 Level fsl-lpuart
52: 0 0 GICv3 262 Level fsl-lpuart
53: 0 0 GICv3 263 Level fsl-lpuart
54: 0 0 GICv3 178 Level 5a880000.adc
55: 49 0 GICv3 257 Level
75: 0 0 GICv3 252 Level 5a020000.spi
76: 0 0 GICv3 253 Level 5a030000.spi
77: 0 0 GICv3 201 Level 5b0d0000.usb
78: 2716 0 GICv3 170 Level mmc0
79: 183 0 GICv3 172 Level mmc1
80: 0 0 GICv3 195 Level eth0
81: 0 0 GICv3 194 Level eth0
83: 0 0 GICv3 198 Level 5b0e0000.usb
84: 0 0 GICv3 103 Level imx8_ddr_perf_pmu
85: 0 0 GICv3 370 Level imx8_ddr_perf_pmu
94: 3065 0 GICv3 119 Level imx_mu_chan[0-0], imx_mu_chan[1-0], imx_mu_chan[3-3]
204: 1 0 gpio-mxc 12 Edge can3 --------------------------------------------------------> this is the one we want to change
212: 0 0 gpio-mxc 20 Edge wakeup-gpio
213: 0 0 gpio-mxc 21 Level pcf85363
214: 0 0 gpio-mxc 22 Level lsm6dsm
IPI0: 3224 4256 Rescheduling interrupts
IPI1: 224 339 Function call interrupts
IPI2: 0 0 CPU stop interrupts
IPI3: 0 0 CPU stop (for crash dump) interrupts
IPI4: 0 0 Timer broadcast interrupts
IPI5: 828 807 IRQ work interrupts
IPI6: 0 0 CPU wake-up interrupts

So is there any change that needs to done with respect to 5.15 linux version?

Regards,
Ankita

[Zhiming_Liu]

Hello,

The second core is index 1, the cpumask_of(2) is the third core. Please try to use cpumask_of(1).

Best Regards,
Zhiming

[ankita_hegde]

Hi,

We even tried cpumask_of(1), still no change, and also if we put a print statement below these lines, even those are not getting printed.

Regards,
Ankita

[Zhiming_Liu]

Hello,

I did same modification in driver. 

Here is test based on 4 core i.MX EVK board, not DXL EVK. This gpio is used by PTN5110.

163: 0 0 8 0 gpio-mxc 19 Level 1-0050

If i plugin USB, the irq handled number will increase.

163: 0 0 18 0 gpio-mxc 19 Level 1-0050

Another interrupt gpio about sd card also can be assigned to core3(index=2)

88: 0 0 1 0 gpio-mxc 12 Edge 30b50000.mmc cd



Best Regards,
Zhiming

[ankita_hegde]

Hi,

But in our case with cpumask_of(1), its still in Core 0:
210: 77 0 gpio-mxc 18 Edge can4

Any idea as to how to fix this? Is there anything like SPI based interrupts are directed only to Core0?

Regards,
Ankita

[Zhiming_Liu]

Hello,

Please share the device tree node and pinctrl about this flexcan 

Best Regards,
Zhiming

[ankita_hegde]

Hi,

DTS node is as below:

&lpspi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpspi2>;
fsl,spi-num-chipselects = <1>;
assigned-clock-rates = <80000000>;
cs-gpios = <&lsio_gpio4 22 GPIO_ACTIVE_HIGH>;
status = "okay";

tcan4x5x0: tcan4x5x@0 {
compatible = "ti,tcan4x5x";
reg = <0>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <1>;
spi-max-frequency = <16000000>;
bosch,mram-cfg = <0x0 3 2 32 10 0 20 10>;
clocks = <&hclk>, <&cclk>;
clock-names = "hclk", "cclk";
interrupt-parent = <&lsio_gpio3>;
interrupts = <12 IRQ_TYPE_EDGE_FALLING>;
data-ready-gpios = <&lsio_gpio3 12 GPIO_ACTIVE_HIGH>;
reset-gpios= <&exp2 12 GPIO_ACTIVE_HIGH>;
iw-tcan-prop;
wakeup-source;
status = "okay";

};
};

Pinctrl:
pinctrl_lpspi2: lpspi2grp {
fsl,pins = <
IMX8DXL_USDHC1_RESET_B_ADMA_SPI2_SCK 0x6000040
IMX8DXL_USDHC1_VSELECT_ADMA_SPI2_SDO 0x6000040
IMX8DXL_USDHC1_WP_ADMA_SPI2_SDI 0x6000040
IMX8DXL_USDHC1_CD_B_LSIO_GPIO4_IO22 0x6000040
IMX8DXL_QSPI0A_DATA3_LSIO_GPIO3_IO12 0xA4000021

>;
};

Regards,
Ankita

[Zhiming_Liu]

Hello,

Referring previous successful gpio case and Documentation/devicetree/bindings/net/can/tcan4x5x.txt, you can try below setting.

tcan4x5x0: tcan4x5x@0 {
compatible = "ti,tcan4x5x";
reg = <0>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <1>;
spi-max-frequency = <16000000>;
bosch,mram-cfg = <0x0 3 2 32 10 0 20 10>;
clocks = <&hclk>, <&cclk>;
clock-names = "hclk", "cclk";
interrupt-parent = <&lsio_gpio3>;
interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
reset-gpios= <&exp2 12 GPIO_ACTIVE_HIGH>;
iw-tcan-prop;
wakeup-source;
status = "okay";

Best Regards,
Zhiming

[ankita_hegde]

Hi,

We tried making it level-triggered but still it's in Core 0.

Regards,
Ankita