K70 LCD P.E. driver question re: Bus width

[crezyoz]

In the component inspector I am able to set the bus width for a monochrome 1bpp/ 2wire interface (PBSIZ = 1). But upon inspecting the registers the PBSIZ register is set to 0, indicating a bus width of 1. If the manual is correct. If I attempt to set the value back to 1 the register then reports it as a 4 bit interface.

Can someone help clear up that confusion for me?

Also, the display I am using states that the pixel clock should always be running. I am new to this type of display but, correct me if I am wrong, the K70 LCD interface can not be set up like that?

[crezyoz]

Thanks again for the response guys. Good thing my client is patient.

In addition to my last post I have found that the ENDIAN mode isn't even set by PE's driver.

Always comes up as LittleEndian.

I am trying to go through it to debug the PE output.

[ProcessorExpert]

Hi,

I'm sorry but currently we cannot guarantee the response time for forum posts. If you feel you found a defect in a product, please use the Support > Technical service request from the top menu.

ad 1) PBSIZ register

There was a problem that the Reference manual was changed since the time of launching the LCDC Processor Expret component was developed. In old RM, the informationcorresponds to what is reported by the debugger (4-bit interface for PBSIZ=1).

Anyway, we have found error in this setting, the code does not initialize these bits properly so we are working on the fix.

ad 2) Also, the display I am using states that the pixel clock should always be running. I am new to this type of display but, correct me if I am wrong, the K70 LCD interface can not be set up like that?

The manual states that this setting is available only in TFT mode (see below) , so it's not supported for mono mode. It might be a problem if your display cannot handle this state.

SCLKIDLE

LSCLK idle enable

Enables/disables LSCLK when VSYNC is idle in TFT mode.

0 Disable LSCLK

1 Enable LSCLK

SCLKSEL

LSCLK select

Selects whether to enable or disable LSCLK in TFT mode when there is no data output.

0 Disable OE and LSCLK in TFT mode when no data output.

1 Always enable LSCLK in TFT mode even if there is no data output.

ad 3) ENDIAN mode isn't even set by PE's driver.

This seems to be a bug, we'll prepare a fix. I'll keep you informed.

Generally, could you please give us more details on the display type you use, your CodeWarrior version and PEx component settings? A sample project or at least processorexpert.pe file with settings would be helpful.

best regards
Petr Hradsky
Processor Expert Support Team

[crezyoz]

Thank you for your response. I realize you can not guarantee a response time. I havemany posts here that are unanswered. But the problem is.. I am working with a manual and an IDE that are both erroneous, which costs me a lot of extra time and my clients a lot of extra money.  The Tech Support response time isn't much better, unfortunately.

Thank you for answering this one.

re: PBSIZ

Does that mean that the 2bpp mode is unavailable for all formats? 

re: LSCLK

In mono mode it runs through the VSYNC interval but it stops during HSYNC. That is the problem. I am using a Planar EL512.256  display.  You can find the reference manual HERE. 

It should be functional in monochrome mode as well. The manual states it is, we selected the K70 for that purpose and we were near PCB layout when I found this problem.

Please do let me know when you have found and fixed issues with the LCDC

Tha manual I downloaded from Freescale, is that the current manual?

Thank you for responding to my post Petr. It is at this stage, new MPU, new IDE, that we really do need direct assistance so we are not spending days discovering errors in Freescale products.

[ProcessorExpert]

regarding PBSIZ:

I'm not sure what do you mean. The PBSIZ configures the width of the bus, not bpp (bits per pixel).

regarding LSCLK:

Yes, according to the manual (the latest on the web that is available is K70P256M150SF3RM Rev. 2, Dec 2011) in mono mode it runs through the VSYNC interval but it stops during HSYNC (see Figure 62-33. LCDC Interface Timing for 4-bit Data Width Gray-Scale Panels). I suppose it's the limitation of the hardware, and we are not aware of any possibility to configure this. It doesn't seem to be clear from the manual of the display if it's a problem. 

The hotfix for the mentioned issues in the component should be available by tomorrow, I'll post it here.

best regards
Petr Hradsky
Processor Expert Support Team

[crezyoz]

"

regarding PBSIZ:

I'm not sure what do you mean. The PBSIZ configures the width of the bus, not bpp (bits per pixel)."

Yes.. I meant 2 bit interface.

thank you for pointing out figure 62-33. However, I am not running a gray scale panel. So I didn't reference that timing diagram.

if I may, I suggest that a clear differentiation about this timing be added to the register documentation for the LSCLK settings.

You're been most helpful Petr.  Thank you.

I am now chasing an example to enable the DDR2 on the TWR board because I have been able to get my mono display to work in TFT mode using 4bpp or 8bpp and I need at least 512kb of RAM. I am searching for the twr_ddr2_script_init() for the K70 tower.  Or any code that will get that up and running.  Can you point me to where that is? I am not using MQX.

[ProcessorExpert · Accepted solution]

Please find attached the hotfix for LCDC_LDD fixing the already mentioned issues.

You can find details in the readme.txt within the archive.

best regards
Petr Hradsky
Processor Expert Support Team

[crezyoz]

Thank you

There is one more non-essential item for another hot fix.

VSYNC. WAIT_2 should be allowed to go to 0 instead of limiting it to a minimum of 1. It is an essential setting when using paticular LCDs.

[ProcessorExpert]

Hello,

please find the attached project with CPU component cofigured to use DDR. Regarding VSYNC, WAIT_2 bitfields, you can  use the following PDD macros to write requested value.

LCDC_PDD_SetVerticalTiming

LCDC_PDD_SetHorizontalTiming

best regards
Vojtech Filip
Processor Expert Support Team