pcie secondary bus reset

[somyaaggarwal08]

I have a board based on mpc8569 processor. I have an end point device connected to pcie bus 00-01 . I want to re-enumerate the pcie device on soft reset. I have set secondary bus reset bit of pcie bridge control register(0x3E) to enable hot reset , However I am unable to re-enumerate the pcie device.

[somyaaggarwal08]

Hi,

I want to implement hot reset feature of pcie. In the mpc8569 manual it is mentioned that in order to implement  hot reset we need to set secondary bus reset bit of pci bridge control register. 

Value of ltssm just after hot reset is 0x33

Also when board is powered off, I am able to enumerate pcie device.

Below is the code snapshot:

pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &brg_ctrl);  
brg_ctrl |= 0x40; //setting hot reset
pci_write_config_word(dev, PCI_BRIDGE_CONTROL, brg_ctrl);
pci_hose_read_config_word(hose, dev, PCI_LTSSM, &ltssm);
printf("Reading link training status... ltssm = 0x%X", ltssm);
udelay(10000);
 //bringing secondary bus out of reset
   brg_ctrl &= FFBF;
  pci_write_config_word(dev, PCI_BRIDGE_CONTROL, brg_ctrl);
  udelay(10000);
  pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &brg_ctrl);

[ufedor]

How exactly the re-enumeration is performed?

What is the LTSSM value just before the re-enumeration attempt?

[ufedor]

You wrote:

> I have set secondary bus reset bit of pcie bridge control register

How exactly this is done?

What is the LTSSM value immediately after the secondary bus reset bit setting?

> I am unable to re-enumerate the pcie device.

Is it ever possible to enumerate the device?

How exactly the re-enumeration is performed?